IP Library Granted Patent US 12,191,245
Granted Patent B2
US 12,191,245 · App. 17/731,861 · Granted Jan 7, 2025

Semiconductor device having a curved part in the printed circuit board

Inventors: Motohito Hori (Nagano, JP); Yoshinari Ikeda (Nagano, JP); Akio Toba (Tokyo, JP); Michio Tamate (Tokyo, JP); Ikuya Sato (Kanagawa, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L23/4985H01L23/49822H01L23/49833H01L24/16H01L24/32H01L24/73H01L25/072H01L2224/16225H01L2224/32225H01L2224/73253H01L2924/182H01L2924/30107
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,191,245
App. No.
17/731,861
Granted
Jan 7, 2025
Kind
B2
Abstract

A semiconductor device includes: an insulated circuit substrate including first and second conductive layers on a top surface side; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board including a first lower-side wiring layer arranged to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate; a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer; a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer; and a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part.

Claims (28)

1. A semiconductor device comprising:

an insulated circuit substrate including first and second conductive layers on a top surface side;

a first semiconductor chip mounted on the first conductive layer;

a second semiconductor chip mounted on the second conductive layer;

a printed circuit board including an insulating layer, a first lower-side wiring layer arranged on one main surface of the insulating layer so as to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged on the one main surface of the insulating layer so as to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate;

a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer;

a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer;

a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part; and

a sealing member provided to seal the first and second semiconductor chips, the printed circuit board, and the first to third connection members.

2. The semiconductor device of claim 1 , wherein the first to third connection members have heights common to each other.

3. The semiconductor device of claim 1 , wherein the curved part has a step having a thickness common to a total thickness of the first semiconductor chip and a bonding material bonding the first semiconductor chip and the first conductive layer to each other.

4. The semiconductor device of claim 1 , wherein the curved part is located in a middle part of the printed circuit board in a longitudinal direction.

5. The semiconductor device of claim 1 , wherein the insulating layer is formed from resin.

6. The semiconductor device of claim 1 , wherein the insulated circuit substrate includes a resin substrate having a top surface on which the first and second conductive layers are deposited.

7. The semiconductor device of claim 6 , further comprising a first external connection terminal integrated with the second conductive layer and externally extending from the sealing member.

8. The semiconductor device of claim 1 , wherein the first lower-side wiring layer is electrically connected to a main electrode of the first semiconductor chip, and

the second lower-side wiring layer is electrically connected to a main electrode of the second semiconductor chip.

9. The semiconductor device of claim 1 , wherein the printed circuit board includes:

a first upper-side wiring layer deposited on a top surface of the insulating layer at a position overlapping with the first lower-side wiring layer via the insulating layer so as to be electrically connected to the first lower-side wiring layer; and

a second upper-side wiring layer deposited on the top surface of the insulating layer at a position overlapping with the second lower-side wiring layer via the insulating layer so as to be electrically connected to the second lower-side wiring layer.

10. The semiconductor device of claim 9 , further comprising a second external connection terminal connected to the first upper-side wiring layer.

11. The semiconductor device of claim 10 , further comprising a third external connection terminal connected to the second upper-side wiring layer.

12. The semiconductor device of claim 9 , wherein the printed circuit board includes:

a third lower-side wiring layer deposited on a bottom surface of the insulating layer and electrically connected to a first main electrode of the first semiconductor chip; and

a third upper-side wiring layer deposited on the top surface of the insulating layer at a position overlapping with the third lower-side wiring layer via the insulating layer so as to be electrically connected to a control electrode of the first semiconductor chip, and

the third lower-side wiring layer and the third upper-side wiring layer have current paths opposite to each other.

13. The semiconductor device of claim 1 , wherein the printed circuit board is provided with a slit at a position corresponding to the curved part.

14. The semiconductor device of claim 1 , wherein the printed circuit board is provided with a notch at a position corresponding to the curved part.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2022
From: HORI, MOTOHITO; IKEDA, YOSHINARI; TOBA, AKIO; TAMATE, MICHIO; SATO, IKUYA
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 059760/0847 →
Priority Claims (1)
JP 2021-100366 · Jun 16, 2021 · national
Continuity (1)
Related Publication 20220406690A1 · Dec 22, 2022
References Cited (6)
US 9196572B2 · Steger et al. · 2015 [cited by applicant]
US 11127714B2 · Nakamura · 2021 [cited by applicant]
US 20160135326A1 · Kim · 2016 [cited by examiner]
US 20210020603A1 · Nakamura · 2021 [cited by applicant]
JP 2010157610A · 2010 [cited by applicant]
JP 202119063A · 2021 [cited by applicant]