Multi-gate semiconductor device with inner spacer and fabrication method thereof
A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.
1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions;
forming a sacrificial gate structure over the fin structure;
forming a gate spacer on sidewalls of the sacrificial gate structure;
etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench;
laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses;
selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer;
performing an anisotropic etching process to remove at least some vertical portions of the insulating layer from the S/D trench, wherein other portions of the insulating layer in the recesses remain; and
growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.
2. The method of claim 1 , wherein the air gaps are laterally between the S/D epitaxial feature and the insulating layer.
3. The method of claim 1 , wherein the insulating layer has a dielectric constant higher than the gate spacer.
4. The method of claim 1 , wherein the insulating layer comprises silicon, oxygen, carbon, and nitrogen.
5. The method of claim 1 , wherein a portion of the insulating layer in the recesses is in contact with lateral ends of the first semiconductor layers, further comprising:
performing an etching process to reduce a thickness of the portion of the insulating layer.
6. The method of claim 1 , further comprising:
removing the sacrificial gate structure, thereby forming a gate trench; and
etching the first semiconductor layers from the gate trench, thereby exposing a portion of the insulating layer in the gate trench, wherein the etching of the first semiconductor layers also reduces a thickness of the portion of the insulating layer.
7. The method of claim 1 , further comprising:
removing the sacrificial gate structure, thereby forming a gate trench;
performing a first etching process, thereby removing the first semiconductor layers from the gate trench and exposing a portion of the insulating layer in the gate trench; and
performing a second etching process to reduce a thickness of the portion of the insulating layer.
8. The method of claim 1 , wherein the growing of the S/D epitaxial feature includes controlling a growth rate of the S/D epitaxial feature, such that the S/D epitaxial feature has concave surfaces exposed in the air gaps and extending away from lateral ends of the first semiconductor layers.
9. The method of claim 1 , wherein the growing of the S/D epitaxial feature includes controlling a growth rate of the S/D epitaxial feature, such that the S/D epitaxial feature has convex surfaces exposed in the air gaps and extending towards lateral ends of the first semiconductor layers.
10. The method of claim 1 , wherein the insulating layer comprises a metal oxide.
11. A method of manufacturing a semiconductor device, comprising:
forming a stack of first type and second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and being alternatingly disposed in a vertical direction;
patterning the stack to form a fin structure;
forming a sacrificial gate structure over the fin structure;
removing at least the first type epitaxial layers from a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure;
forming an insulating layer on lateral ends of the first type epitaxial layers;
forming an S/D epitaxial feature in contact with the insulating layer and the second type epitaxial layers, wherein the insulating layer interposes the S/D epitaxial feature and the first type epitaxial layers, and wherein the S/D epitaxial feature traps air gaps laterally between the S/D epitaxial feature and the insulating layer;
removing the sacrificial gate structure and the first type epitaxial layers, resulting in a gate trench; and
partially etching a portion of the insulating layer exposed in the gate trench.
12. The method of claim 11 , wherein the insulating layer has a dielectric constant larger than 5.
13. The method of claim 11 , wherein the insulating layer includes silicon carbon oxynitride.
14. The method of claim 11 , wherein after the partially etching of the portion of the insulating layer, the portion of the insulating layer exposed in the gate trench has a thickness less than other portions of the insulating layer in contact with the second type epitaxial layers.
15. The method of claim 11 , further comprising:
forming a metal gate stack in the gate trench, wherein the insulating layer interposes the metal gate stack and the air gaps.
16. The method of claim 11 , further comprising:
forming a gate spacer on sidewalls of the sacrificial gate structure, wherein a portion of the gate spacer is exposed in the air gaps.
17. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions;
forming a sacrificial gate structure over the fin structure;
forming a gate spacer on sidewalls of the sacrificial gate structure;
etching a region of the fin structure not covered by the sacrificial gate structure and the gate spacer, thereby forming a trench;
laterally etching the first semiconductor layers through the trench, thereby forming recesses;
depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses;
growing an epitaxial feature in the trench, thereby trapping at least an air gap in one of the recesses;
removing the sacrificial gate structure, thereby forming a gate trench;
removing the first semiconductor layers from the gate trench to expose a first portion of the insulating layer in the gate trench; and
forming a metal gate stack in the gate trench and in contact with the first portion of the insulating layer,
wherein the insulating layer includes a second portion in contact with the epitaxial feature, and a thickness of the second portion is larger than a thickness of the first portion.
18. The method of claim 17 , wherein the second portion of the insulating layer extends vertically along a sidewall of the epitaxial feature.
19. The method of claim 17 , wherein the air gap has a dome shape.
20. The method of claim 17 , wherein a ratio of a dielectric constant of the insulating layer over a dielectric constant of the gate spacer ranges from about 1.5 to about 3.