IP Library › Granted Patent US 12,191,836
Granted Patent B2
US 12,191,836 · App. 17/818,442 · Granted Jan 7, 2025

Bandpass filter, touch driver including the same, and method of bandpass filtering

Inventor: Moon Jae Jeong (Hwaseong-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H03H7/12G06F3/04182
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,191,836
App. No.
17/818,442
Granted
Jan 7, 2025
Kind
B2
Abstract

A bandpass filter comprises first and second input terminals configured to receive a plurality of radio frequency signals having a phase difference, first and second load resistors connected in series to the first and second input terminals, respectively, a first switching unit connected in series to the first and second load resistors, a capacitor unit connected in series to the first switching unit, a second switching unit connected between the capacitor unit and a ground, and first and second output terminals connected between the first switching unit and the first and second load resistors, respectively.

Claims (131)

1. A bandpass filter comprising:

a first input terminal and a second input terminal, the first input terminal configured to receive a first radio frequency signal having a first phase and the second input terminal configured to receive a second radio frequency signal having a second phase different from the first phase;

a first load resistor connected in series to the first input terminal;

a second load resistor connected in series to the second input terminal;

a first switching unit connected in series to the first load resistor and the second load resistor;

a capacitor unit connected in series to the first switching unit;

a second switching unit connected between the capacitor unit and a ground;

a first output terminal connected between the first switching unit and the first load resistor; and

a second output terminal connected between the first switching unit and the second load resistor.

2. The bandpass filter of claim 1 , wherein:

the first switching unit and the second switching unit are turned on based on clock signals having the same phase to connect the first load resistor and the capacitor unit in series to the ground or to connect the second load resistor and the capacitor unit in series to the ground.

3. The bandpass filter of claim 2 , wherein:

one switching element of the first switching unit and one switching element of the second switching unit are turned on based on a clock signal having the first phase and are connected to one capacitor of the capacitor unit; and

another switching element of the first switching unit and another switching element of the second switching unit are turned on based on the clock signal having the first phase and are connected to another capacitor of the capacitor unit.

4. The bandpass filter of claim 1 , wherein the first switching unit comprises:

at least one first-first switching element turned on based on a first clock signal having a first phase;

at least one first-second switching element turned on based on a second clock signal having the second phase delayed from the first phase;

at least one first-third switching element turned on based on a third clock signal having a third phase delayed from the second phase; and

at least one first-fourth switching element turned on based on a fourth clock signal having a fourth phase delayed from the third phase.

5. The bandpass filter of claim 4 , wherein the capacitor unit comprises:

a first capacitor connected to the first load resistor through the at least one first-first switching element, and the first capacitor is connected to the second load resistor through the at least one first-third switching element;

a second capacitor connected to the first load resistor through the at least one first-second switching element, and the second capacitor is connected to the second load resistor through the at least one first-fourth switching element;

a third capacitor connected to the first load resistor through the at least one first-third switching element, and the third capacitor is connected to the second load resistor through the at least one first-first switching element; and

a fourth capacitor connected to the first load resistor through the at least one first-fourth switching element, and the fourth capacitor is connected to the second load resistor through the at least one first-second switching element.

6. The bandpass filter of claim 5 , wherein the second switching unit comprises:

at least one second-first switching element turned on based on the first clock signal having the first phase;

at least one second-second switching element turned on based on the second clock signal having the second phase delayed from the first phase;

at least one second-third switching element turned on based on the third clock signal having the third phase delayed from the second phase; and

at least one second-fourth switching element turned on based on the fourth clock signal having the fourth phase delayed from the third phase.

7. The bandpass filter of claim 6 , wherein:

the first capacitor is connected to the ground through the second-first switching element or the second-third switching element;

the second capacitor is connected to the ground through the second-second switching element or the second-fourth switching element;

the third capacitor is connected to the ground through the second-third switching element or the second-first switching element; and

the fourth capacitor is connected to the ground through the second-fourth switching element or the second-second switching element.

8. The bandpass filter of claim 6 , further comprising:

a third input terminal and a fourth input terminal configured to receive a plurality of radio frequency signals having a phase different from those of the radio frequency signals of the first and second input terminals;

a third load resistor connected to the third input terminal;

a fourth load resistor connected to the fourth input terminal;

a third switching unit connected between the third load resistor and the capacitor unit or between the fourth load resistor and the capacitor unit;

a fourth switching unit connected between the capacitor unit and the ground;

a third output terminal connected between the third switching unit and the third load resistor; and

a fourth output terminal connected between the third switching unit and the fourth load resistor.

9. The bandpass filter of claim 8 , wherein the third switching unit comprises:

at least one third-first switching element turned on based on the first clock signal having the first phase;

at least one third-second switching element turned on based on the second clock signal having the second phase delayed from the first phase;

at least one third-third switching element turned on based on the third clock signal having the third phase delayed from the second phase; and

at least one third-fourth switching element turned on based on the fourth clock signal having the fourth phase delayed from the third phase.

10. The bandpass filter of claim 9 , wherein the fourth switching unit comprises:

at least one fourth-first switching element turned on based on the first clock signal having the first phase;

at least one fourth-second switching element turned on based on the second clock signal having the second phase delayed from the first phase;

at least one fourth-third switching element turned on based on the third clock signal having the third phase delayed from the second phase; and

at least one fourth-fourth switching element turned on based on the fourth clock signal having the fourth phase delayed from the third phase.

11. The bandpass filter of claim 10 , wherein:

the first capacitor is connected to the third load resistor through the third-second switching element, and the first capacitor is connected to the fourth load resistor through the third-fourth switching element;

the second capacitor is connected to the third load resistor through the third-third switching element, and the second capacitor is connected to the fourth load resistor through the third-first switching element;

the third capacitor is connected to the third load resistor through the third-fourth switching element, and the third capacitor is connected to the fourth load resistor through the third-second switching element; and

the fourth capacitor is connected to the third load resistor through the third-first switching element, and the fourth capacitor is connected to the fourth load resistor through the third-third switching element.

12. The bandpass filter of claim 10 , wherein:

the first capacitor is connected to the ground through the fourth-second switching element or the fourth-fourth switching element;

the second capacitor is connected to the ground through the fourth-third switching element or the fourth-first switching element;

the third capacitor is connected to the ground through the fourth-fourth switching element or the fourth-second switching element; and

the fourth capacitor is connected to the ground through the fourth-first switching element or the fourth-third switching element.

13. The bandpass filter of claim 1 , wherein the first switching unit comprises:

at least one first-first switching element turned on based on a first clock signal having a first phase;

at least one first-second switching element turned on based on a second clock signal having a second phase delayed from the first phase;

at least one first-third switching element turned on based on a third clock signal having a third phase delayed from the second phase;

at least one first-fourth switching element turned on based on a fourth clock signal having a fourth phase delayed from the third phase;

at least one first-fifth switching element turned on based on a fifth clock signal having a fifth phase delayed from the fourth phase;

at least one first-sixth switching element turned on based on a sixth clock signal having a sixth phase delayed from the fifth phase;

at least one first-seventh switching element turned on based on a seventh clock signal having a seventh phase delayed from the sixth phase; and

at least one first-eighth switching element turned on based on an eighth clock signal having an eighth phase delayed from the seventh phase.

14. The bandpass filter of claim 13 , wherein the capacitor unit comprises:

a first capacitor connected to the first load resistor through the at least one first-first switching element, and the first capacitor is connected to the second load resistor through the at least one first-fifth switching element;

a second capacitor connected to the first load resistor through the at least one first-second switching element, and the second capacitor is connected to the second load resistor through the at least one first-sixth switching element;

a third capacitor connected to the first load resistor through the at least one first-third switching element, and the third capacitor is connected to the second load resistor through the at least one first-seventh switching element;

a fourth capacitor connected to the first load resistor through the at least one first-fourth switching element, and the fourth capacitor is connected to the second load resistor through the at least one first-eighth switching element;

a fifth capacitor connected to the first load resistor through the at least one first-fifth switching element, and the fifth capacitor is connected to the second load resistor through the at least one first-first switching element;

a sixth capacitor connected to the first load resistor through the at least one first-sixth switching element, and the sixth capacitor is connected to the second load resistor through the at least one first-second switching element;

a seventh capacitor connected to the first load resistor through the at least one first-seventh switching element, and the seventh capacitor is connected to the second load resistor through the at least one first-third switching element; and

an eighth capacitor connected to the first load resistor through the at least one first-eighth switching element, and the eighth capacitor is connected to the second load resistor through the at least one first-fourth switching element.

15. The bandpass filter of claim 14 , wherein the second switching unit comprises:

at least one second-first switching element turned on based on the first clock signal having the first phase;

at least one second-second switching element turned on based on the second clock signal having the second phase delayed from the first phase;

at least one second-third switching element turned on based on the third clock signal having the third phase delayed from the second phase;

at least one second-fourth switching element turned on based on the fourth clock signal having the fourth phase delayed from the third phase;

at least one second-fifth switching element turned on based on the fifth clock signal having the fifth phase delayed from the fourth phase;

at least one second-sixth switching element turned on based on the sixth clock signal having the sixth phase delayed from the fifth phase;

at least one second-seventh switching element turned on based on the seventh clock signal having the seventh phase delayed from the sixth phase; and

at least one second-eighth switching element turned on based on the eighth clock signal having the eighth phase delayed from the seventh phase.

16. The bandpass filter of claim 15 , further comprising:

third and fourth input terminals configured to receive a second plurality of radio frequency signals having a second phase difference different from the phase difference of the plurality of radio frequency signals the first and second input terminals are configured to receive;

a third load resistor connected to the third input terminal;

a fourth load resistor connected to the fourth input terminal;

a third switching unit connected between the third load resistor and the capacitor unit or between the fourth load resistor and the capacitor unit;

a fourth switching unit connected between the capacitor unit and the ground;

a third output terminals connected between the third switching unit and the third load resistor; and

a fourth output terminal connected between the third switching unit and the fourth load resistor.

17. A bandpass filter comprising:

first input terminal configured to receive a first radio frequency signal having a first phase and second input terminal configured to receive a second radio frequency signal having a second phase different from the first phase;

a first load resistor connected in series to the first input terminal;

a second load resistor connected in series to the second input terminal;

a first switching unit configured to connect the first load resistor or the second load resistor to each of a plurality of paths;

a capacitor unit disposed on each of the plurality of paths and connected to the first switching unit; and

a second switching unit disposed on each of the plurality of paths and connected between the capacitor unit and a ground.

18. The bandpass filter of claim 17 , further comprising:

a first output terminal connected between the first switching unit and the first load resistor; and

a second output terminal connected between the first switching unit and the second load resistor.

19. The bandpass filter of claim 17 , wherein:

a switching element of the first switching unit and a switching element of the second switching unit disposed on one path among the plurality of paths are turned on based on clock signals having the same phase to connect the first load resistor and the capacitor unit in series to the ground or to connect the second load resistor and the capacitor unit in series to the ground.

20. A touch driver comprising:

a bandpass filter configured to receive a radio frequency signal and filter a specific frequency band;

a first mixer configured to receive an output of the bandpass filter and output frequency signals having a first phase and a second phase opposite to the first phase;

a second mixer configured to receive an output of the bandpass filter and output frequency signals having a third phase different from the first phase and a fourth phase opposite to the third phase; and

a complex bandpass filter configured to receive outputs of the first and second mixers and select and output one of a positive frequency component and a negative frequency component,

wherein the complex bandpass filter comprises:

a first input terminal and a second input terminal, the first input terminal and the second input terminal configured to receive a plurality of radio frequency signals having a phase difference;

a first load resistor connected in series to the first input terminal;

a second load resistor connected in series to the second input terminal;

a first switching unit connected in series to the first load resistor and the second load resistor;

a capacitor unit connected in series to the first switching unit;

a second switching unit connected between the capacitor unit and a ground;

a first output terminal connected between the first switching unit and the first load resistor; and

a second output terminal connected between the first switching unit and the second load resistor.

21. A method comprising:

receiving a plurality of radio frequency signals using at least two input terminals including a first input terminal configured to receive a positive frequency component having a first phase and a second input terminal configured to receive a negative frequency component having a second phase opposite to the first phase;

selecting one of the positive frequency component and the negative frequency component using a circuit comprising:

at least two load resistors connected in series to the at least two input terminals;

a first switching unit connected in series to the at least two load resistors;

a capacitor unit connected in series to the first switching unit;

a second switching unit connected between the capacitor unit and a ground; and

outputting the selected one of the positive frequency component and the negative frequency component using at least two output terminals, the at least two output terminals connected between the first switching unit and the at least two load resistors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2022
From: JEONG, MOON JAE
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 060755/0433 →
Priority Claims (1)
KR 10-2021-0140003 · Oct 20, 2021 · national
Continuity (1)
Related Publication 20230121263A1 · Apr 20, 2023
References Cited (26)
US 9014653B2 · Madadi et al. · 2015 [cited by applicant]
US 9136815B2 · Aggarwal · 2015 [cited by examiner]
US 10146379B2 · Wang · 2018 [cited by examiner]
US 20130335163A1 · Aggarwal et al. · 2013 [cited by applicant]
US 20140080436A1 · Madadi et al. · 2014 [cited by applicant]
US 20150133068A1 · Aggarwal et al. · 2015 [cited by applicant]
US 20190215030A1 · Nabki et al. · 2019 [cited by applicant]
US 20200119766A1 · Nabki et al. · 2020 [cited by applicant]
US 20200358474A1 · Nabki et al. · 2020 [cited by applicant]
US 20210203379A1 · Nabki et al. · 2021 [cited by applicant]
US 20220337285A1 · Nabki et al. · 2022 [cited by applicant]
EP 2871774 · 2015 [cited by applicant]
WO 9807127 · 1998 [cited by applicant]
WO 2019000075 · 2019 [cited by applicant]
WO 2019211997 · 2019 [cited by applicant]
Partial European Search Report dated Mar. 22, 2023 in corresponding European Patent Application No. 22202605.6 (18 pages). [cited by applicant]
Mirzaei, et al., “A Low-Power Process-Scalable Super-Heterodyne Receiver With Integrated High-Q Filters”, IEEE Journal of Solid-State Circuits, vol. 46. No. 12, Dec. 2011, pp. 2920-2932. [cited by applicant]
Ghaffari, et al., “Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification”, IEEE Journal of Solid-State Circuits, vol. 46, No. 5, May 2011, pp. 998-1010. [cited by applicant]
Tohidian, et al., “A 2mW 800MS/s 7th-Order Discrete-Time IIR Filter with 400kHz-to-30MHz BW and 100dB Stop-Band Rejection in 65nm CMOS”, 2013 IEEE International Solid-State Circuits Conference, Session 10, Analog Techni… [cited by applicant]
Madadi, et al., “A 65nm CMOS High-IF Superheterodyne Receiver with a High-Q Complex BPF”, 2013 IEEE Radio Frequency Integrated Circuits Symposium, pp. 323-326. [cited by applicant]
Tohidian, et al., “A Fully Integrated Discrete-Time Superheterodyne Receiver”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, No. 2, Feb. 2017, pp. 635-647. [cited by applicant]
Tohidian, et al., “A Fully Integrated Highly Reconfigurable Discrete-Time Super-Heterodyne Receiver” 2014 IEEE International Solid-State Circuits Conference, Session 3, RF Techniques, 3 pages. [cited by applicant]
Madadi, et al., “High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection”, IEEE Journal of Solid-State Circuits, vol. 51, No. 2, Feb. 2016, pp. 332-347. [cited by applicant]
Madadi, et al., “A TDD FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS”, 2015 Symposium on VLSI Circuits Digest of Technical Papers, pp. C308-C309. [cited by applicant]
Tohidian, et al., “Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter”, IEEE Journal of Solid-State Circuits, vol. 49, No. 11, Nov. 2014, pp. 2575-2587. [cited by applicant]
Madadi, et al., “Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers”, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 62, No. 8, Aug. 2015, pp. 2114-2121. [cited by applicant]