Hybrid phase-interpolator
View Patent ↗A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.
1. A phase interpolator comprising:
digital to analog converter configured to, responsive to a control code, output a first value and a second value, wherein the first value is different than the second value;
a first current mirror configured to generate a first current that is proportional to the first value;
a second current mirror configured to generate a second current that is proportional to the second value;
a first FET pair comprising a first FET, with a first gate terminal receiving a clock signal, and a second FET having second gate terminal receiving an inverted clock signal such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror to receive the first current;
a second FET pair comprising a third FET, with a third gate terminal receiving the inverted clock signal, and a fourth FET having fourth gate terminal receiving the clock signal such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror to receive the second current, wherein the clock signal and the inverted clock signal are the only clock signals provide to gates terminals of FET pairs in the phase interpolator;
a first output terminal, configured to output a phase adjusted clock signal as compared to the clock signal, connected to a first drain terminal of the first FET and a third drain terminal of the third FET;
a second output terminal, configured to output an inverted version of the phase adjusted clock signal, connected to a second drain terminal of the second FET and a fourth drain terminal of the fourth FET.
2. The phase interpolator of claim 1 wherein the first value is different than the second value.
3. The phase interpolator of claim 2 wherein the first value is inversely proportional to the second value.
4. The phase interpolator of claim 1 wherein the control code controls the amount of phase adjustment in the phase adjusted clock signal.
5. The phase interpolator of claim 1 further comprising a degeneration resistor connected to each source terminal.
6. The phase interpolator of claim 1 wherein the phase interpolator requires only the clock signal and the inverted clock signal.
7. The phase interpolator of claim 1 wherein the first current mirror has a first mirror ratio and the second current mirror has a second mirror ratio and the first mirror ratio is different than the second mirror ratio.
8. A method for adjusting phase of an input signal with a phase interpolator comprising:
receiving the input signal, an inverted input signal and a control code indicating an amount of phase adjustment to apply to the input signal;
generating a first current based on the control code and generating a second current based on the control code such that the first current is not equal to the second current;
providing the first current to a first FET pair such that flow of the first current through FETs that form the first FET pair is controlled by the input signal and the inverted input signal;
providing the second current to second FET pair such that flow of the second current through FETs that form the second FET pair is controlled by the input signal and the inverted input signal, wherein the first FET pair and the second FET pair are the only FET pairs in the phase interpolator and the method for adjusting phase in the phase interpolator requires only the input signal and the inverted input signal to be provided to the first FET pair and the second FET pair;
forming a phase adjusted output signal from a first current of the first FET pair and a second FET current of the second FET pair; and
forming an inverted version of the phase adjusted output signal from a second FET current of the first FET pair and a second FET current of the second FET pair.
9. The method of claim 8 wherein the control code is a digital value and the control code is converted to a first analog value and a second analog value by one or more digital to analog converters.
10. The method of claim 8 wherein generating the first current based on the control code is performed by a first current mirror and generating the second current based on the control code is performed by a second current mirror.
11. The method of claim 8 wherein the amount of phase adjustment is also determined by mirror ratios of the first current mirror and the second current mirror.
12. The method of claim 8 further comprising converting the input signal and the inverted input signal from a square wave signal to a rounded sine wave type signal using one or more degeneration resistors and capacitors.
13. The method of claim 8 further comprising processing the phase adjusted output signal with an inverter to form a square wave signal from the phase adjusted output signal.
14. The method of claim 8 wherein the input signal is a clock signal.
15. A phase interpolator for adjusting phase of an input signal comprising:
a first current source configured to generate a first current;
a second current source configured to generate a second current, such that the first current is different than the second current and the difference between the first current and the second current is based on a control value;
a switching block configured to receive the first current, the second current, the input signal, and an inverted input signal and, selectively perform switching, controlled by the input signal and inverted input signal, to create and output at least an output signal which is a delayed version of the input signal such that an amount of delay in the output signal is controlled by the difference between the first current and the second current, wherein the switching, in the switching block of the phase interpolator is controlled by only the input signal and the inverted input signal.
16. The phase interpolator of claim 15 wherein the first current source comprises a first current mirror and the second current source comprises a second current mirror.
17. The phase interpolator of claim 15 wherein the control value is processed by a DAC to generate a first signal and a second signal, such that the first signal controls a magnitude of the first current and the second signal controls a magnitude of the second current.
18. The phase interpolator of claim 15 wherein the switching block comprises two cross connected FET pairs with gate terminals configured to receive one of the input signal and inverted input signal.
19. The phase interpolator of claim 15 further comprising one or more degeneration resistors configured to decrease a rate of change of the input signal and inverted input signal.
20. The phase interpolator of claim 15 wherein the input signal is a clock signal.