Slope analog-to-digital converter and a method for analog-to-digital conversion of an analog input signal
A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.
1. A slope analog-to-digital converter, ADC, for converting an analog input signal to a digital representation, said ADC comprising:
an input unit comprising a sampling capacitor, wherein the input unit is configured to receive the analog input signal during an initial period for obtaining a sampled value of the analog input signal and wherein the input unit is configured to, during a conversion period, hold the sampled value of the analog input signal across the sampling capacitor between a first terminal and a second terminal of the sampling capacitor; and
a comparator which is configured to determine a most significant bit of the analog input signal during the initial period;
wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.
2. The ADC according to claim 1 , wherein the input unit is a track and hold unit and wherein the input unit is configured to track the received analog input signal thereby obtaining the sampled value of the analog input signal.
3. The ADC according to claim 1 , wherein the ADC comprises at least one switch for selectively controlling an input to the comparator, during the conversion period and in dependence of the determined most significant bit, thereby connecting the input to the comparator to the first terminal or the second terminal of the sampling capacitor.
4. The ADC according to claim 3 , wherein the at least one switch comprises a plurality of switches for selectively controlling which of the first terminal and the second terminal of the sampling capacitor is connected to the input to the comparator during the conversion period.
5. The ADC according to claim 4 , wherein the sampling capacitor is configured to be connected to a first terminal of the input to the comparator regardless of the determined most significant bit.
6. The ADC according to claim 5 , wherein the plurality of switches is configured to control the first terminal or the second terminal of the sampling capacitor not being connected to the input to the comparator during the conversion period to be connected to the slope signal, and wherein the comparator is configured to be further connected at the input to a reference signal during the conversion period.
7. The ADC according to claim 1 , wherein the comparator is configured to compare a combination of the sampled value and the slope signal to a first fixed reference voltage independently of the determined most significant bit.
8. The ADC according to claim 4 , wherein the plurality of switches is configured to selectively control one of the first terminal and the second terminal of the sampling capacitor to be connected to the input to the comparator, wherein the first terminal of the sampling capacitor is selectively connected to a first terminal of the input to the comparator and the second terminal of the sampling capacitor is selectively connected to a second terminal of the input to the comparator, and wherein the plurality of switches is further configured to selectively connect a slope signal to the first terminal or the second terminal of the comparator, such that the input to the comparator is connected to one of the capacitor terminals and a slope signal.
9. The ADC according to claim 3 , wherein the at least one switch is configured to selectively control whether the terminal of the sampling capacitor which is not connected to the input to the comparator is to be connected to ground or to a second fixed reference voltage.
10. The ADC according to claim 1 , wherein the analog input signal is a differential analog input signal comprising a first analog input signal and a second analog input signal and wherein the comparator is configured to receive the first analog input signal and the second analog input signal on a first terminal and a second terminal of the input to the comparator, respectively, during the initial period.
11. The ADC according to claim 1 , wherein the ADC is configured to provide a slope signal which corresponds to levels of the sampled value encompassing more than half of possible values of the digital representation so as to provide a check of determination of the most significant bit.
12. A time-interleaved analog-to-digital converter, ADC, comprising:
a plurality of slope ADCs according to claim 1 , wherein the plurality of slope ADCs are configured to receive the analog input signal successively in time.