IP Library › Granted Patent US 12,191,987
Granted Patent B2
US 12,191,987 · App. 18/388,461 · Granted Jan 7, 2025

Technologies for dynamically managing resources in disaggregated accelerators

Inventors: Francesc Guim Bernat (Barcelona, ES); Susanne M. Balle (Hudson, NH); Rahul Khanna (Portland, OR); Sujoy Sen (Beaverton, OR); Karthik Kumar (Chandler, AZ)
Assignee: Intel Corporation
H04L43/08G02B6/3882G02B6/3893G02B6/3897G02B6/4292G02B6/4452G06F1/183G06F1/20G06F3/0613G06F3/0625G06F3/064G06F3/0653G06F3/0655G06F3/0664G06F3/0665G06F3/0673G06F3/0679G06F3/0683G06F3/0688G06F3/0689G06F8/65G06F9/4401G06F9/544G06F12/109G06F12/1408G06F13/1668G06F13/4022G06F13/4068G06F13/409G06F15/161G06F16/1748G06F16/9014G08C17/02G11C5/02G11C7/1072G11C11/56G11C14/0009H03M7/3086H03M7/4056H03M7/4081H04B10/25891H04L41/145H04L43/0817H04L43/0876H04L43/0894H04L49/00H04L49/25H04L49/357H04L49/45H04L67/02H04L67/306H04L69/04H04L69/329H04Q11/0003H05K7/1442B25J15/0014B65G1/0492G05D23/1921G05D23/2039G06F3/061G06F3/0611G06F3/0616G06F3/0619G06F3/0631G06F3/0638G06F3/0647G06F3/0658G06F3/0659G06F3/067G06F9/5016G06F9/5044G06F9/505G06F9/5072G06F9/5077G06F11/141G06F11/3414G06F12/0862G06F12/0893G06F12/10G06F13/161G06F13/1694G06F13/42G06F13/4282G06F15/8061G06F2209/5019G06F2209/5022G06F2212/1008G06F2212/1024G06F2212/1041G06F2212/1044G06F2212/152G06F2212/202G06F2212/401G06F2212/402G06F2212/7207G06Q10/06G06Q10/06314G06Q10/087G06Q10/20G06Q50/04G07C5/008G08C2200/00G11C5/06H03M7/30H03M7/3084H03M7/40H03M7/4031H03M7/6005H03M7/6023H04B10/25H04J14/00H04L9/0643H04L9/14H04L9/3247H04L9/3263H04L12/2809H04L41/024H04L41/046H04L41/0813H04L41/082H04L41/0896H04L41/12H04L41/147H04L41/5019H04L43/065H04L43/16H04L45/02H04L45/52H04L47/24H04L47/38H04L47/765H04L47/782H04L47/805H04L47/82H04L47/83H04L49/15H04L49/555H04L61/00H04L67/10H04L67/1004H04L67/1008H04L67/1012H04L67/1014H04L67/1029H04L67/1034H04L67/1097H04L67/12H04L67/34H04L67/51H04Q1/04H04Q11/00H04Q11/0005H04Q2011/0037H04Q2011/0041H04Q2011/0052H04Q11/0062H04Q11/0071H04Q2011/0073H04Q2011/0079H04Q2011/0086H04Q2213/13523H04Q2213/13527H04W4/023H04W4/80H05K1/0203H05K1/181H05K5/0204H05K7/1418H05K7/1421H05K7/1422H05K7/1447H05K7/1461H05K7/1485H05K7/1487H05K7/1489H05K7/1491H05K7/1492H05K7/1498H05K7/2039H05K7/20709H05K7/20727H05K7/20736H05K7/20745H05K7/20836H05K13/0486H05K2201/066H05K2201/10121H05K2201/10159H05K2201/10189Y02D10/00Y02P90/30Y04S10/50Y04S10/52Y10S901/01
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Quick Facts
Patent No.
US 12,191,987
App. No.
18/388,461
Granted
Jan 7, 2025
Kind
B2
Abstract

Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

Claims (105)

1. An accelerator device comprising:

an application specific integrated circuit (ASIC) that includes multiple logic portions, wherein the multiple logic portions are configurable to use at least one resource to process respective workloads; and

circuitry to;

identify a first resource utilization amount associated with at least one resource of the accelerator device, and a first resource utilization amount reserved for use by a first logic portion to process a workload,

identify a limit to the first resource utilization amount that limits utilization of the at least one resource by the first logic portion as the first logic portion processes the workload,

monitor the utilization of the at least one resource by the first logic portion as the workload is processed, and

report the utilization of the at least one resource.

2. The accelerator device of claim 1 , wherein the circuitry is further to determine whether the utilization of the at least one resource satisfies the first resource utilization amount, and wherein to report the utilization comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.

3. The accelerator device of claim 1 , wherein the circuitry is to:

receive an adjustment to the first resource utilization amount; and

apply an adjustment to the first resource utilization amount to determine a second resource utilization amount associated with the at least one resource, and a second resource utilization amount reserved for use by the first logic portion to process the workload.

4. The accelerator device of claim 1 , wherein to receive the workload comprises to receive a designation of a logic portion to process the workload.

5. The accelerator device of claim 1 , wherein to receive the workload comprises to receive a bit stream indicative of the workload to be processed.

6. The accelerator device of claim 1 , wherein the first resource utilization amount reserved for use by the first logic portion is based on an amount of processing throughput reserved for use by the first logic portion.

7. The accelerator device of claim 1 , wherein the first resource utilization amount reserved for use by the first logic portion is based on an amount of memory reserved for use by the first logic portion, the memory to include dynamic random access memory.

8. The accelerator device of claim 1 , wherein the first resource utilization amount reserved for use by the first logic portion is based on an amount of data storage reserved for use by the first logic portion.

9. The accelerator device of claim 1 , wherein the first resource utilization amount reserved for use by the first logic portion is based on an amount of network bandwidth reserved for use by the first logic portion.

10. The accelerator device of claim 1 , wherein to identify the first resource utilization amount reserved for use by the first logic portion comprises to receive an identifier of a class of service associated with an amount of a resource reserved for use by the first logic portion.

11. The accelerator device of claim 1 , further comprising the circuitry to:

identify a second resource utilization amount associated with the at least one resource, and a second resource utilization amount reserved for use by a second logic portion from among the multiple logic portions to process a second workload; and

identify a limit to the second resource utilization amount that limits utilization of the at least one resource by the second logic portion as the second logic portion processes the second workload.

12. The accelerator device of claim 1 , further comprising:

a second ASIC that includes second multiple logic portions, wherein the second multiple logic portions are configurable to use at least one second resource to process respective workloads; and

the circuitry to;

identify a second resource utilization amount associated with the at least one second resource, and a second resource utilization amount to be reserved for use by a first logic portion from among the multiple second logic portions to process a second workload, and

identify a limit to the second resource utilization amount that limits utilization of the at least one resource by the second logic portion as the second logic portion processes the second workload.

13. The accelerator device of claim 1 , wherein the accelerator device is located on a server included in a data center.

14. One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, when executed, cause an accelerator device to:

receive a workload to be executed by a first logic portion of a plurality of logic portions of an application specific integrated circuit (ASIC) of the accelerator device, the plurality of logic portions capable of processing respective workloads;

identify a first resource utilization amount associated with at least one resource of the accelerator device, and a first resource utilization amount reserved for use by a first logic portion to process a workload;

identify a limit to the first resource utilization amount that limits utilization of the at least one resource by the first logic portion as the first logic portion processes the workload;

monitor the utilization of the at least one resource by the first logic portion as the workload is processes; and

report the utilization of the at least one resource.

15. The one or more non-transitory machine-readable storage media of claim 14 , wherein the plurality of instructions, when executed, further cause the accelerator device to:

determine whether the utilization of the at least one resource satisfies the first resource utilization amount;

wherein to report the utilization comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.

16. The one or more non-transitory machine-readable storage media of claim 14 , wherein the plurality of instructions, when executed, further cause the accelerator device to:

receive an adjustment to the first resource utilization amount; and

apply the adjustment to the first resource utilization amount to determine a second resource utilization amount associated with the at least one resource, and a second resource utilization amount reserved for use by the first logic portion to process the workload.

17. The one or more non-transitory machine-readable storage media of claim 14 , wherein to receive the workload comprises to receive a designation of a logic portion to process the workload.

18. The one or more non-transitory machine-readable storage media of claim 14 , wherein to receive the workload comprises to receive a bit stream indicative of the workload to be processed.

19. The one or more non-transitory machine-readable storage media of claim 14 , wherein the first resource utilization amount reserved for use by the first logic portion is based on an amount of processing throughput reserved for use by the first logic portion.

20. The one or more non-transitory machine-readable storage media of claim 14 , wherein the first resource utilization amount reserved for use by the first logic portion is based on an amount of memory reserved for use by the first logic portion, the memory to include dynamic random access memory.

21. The one or more non-transitory machine-readable storage media of claim 14 , wherein the first resource utilization amount reserved for use by the first logic portion is based on an amount of data storage reserved for use by the first logic portion.

22. The one or more non-transitory machine-readable storage media of claim 14 , wherein the first resource utilization amount reserved for use by the first logic portion is based on an amount of network bandwidth reserved for use by the first logic portion.

23. The one or more non-transitory machine-readable storage media of claim 14 , wherein to identify the first resource utilization amount comprises to receive resource utilization data indicative of the first resource utilization amount from a processor of a first compute device that is assigned to process a portion of the workload.

24. The one or more non-transitory machine-readable storage media of claim 14 , wherein the plurality of instructions, when executed, further cause the accelerator device to:

identify a second resource utilization amount associated with the at least one resource, and a second resource utilization amount reserved for use by a second logic portion from among the plurality of logic portions to process a second workload; and

identify a limit to the second resource utilization amount that limits utilization of the at least one resource by the second logic portion as the second logic portion processes the second workload.

25. The one or more non-transitory machine-readable storage media of claim 14 , wherein the plurality of instructions, when executed, further cause the accelerator device to:

receive a second workload to be processed by a first logic portion of a second plurality of logic portions of a second ASIC of the accelerator device, the second plurality of logic portions capable of processing respective workloads;

identify a second resource utilization amount associated with at least one second resource of the accelerator device, and a second resource utilization amount reserved for use by the first logic portion to process the second workload; and

identify a limit to the second resource utilization amount that limits utilization of the at least one resource by the second logic portion as the second logic portion processes the second workload.

26. The one or more non-transitory machine-readable storage media of claim 14 , wherein the accelerator device is located on a server included in a data center.

27. A method comprising:

receiving, by an accelerator device, a workload to be executed by a first logic portion of a plurality of logic portions of an application specific integrated circuit (ASIC) of the accelerator device, the plurality of logic portions capable of processing respective workloads;

identifying a first resource utilization amount associated with at least one resource of the accelerator device, and a first resource utilization amount reserved for use by a first logic portion to process a workload;

identifying a limit to the first resource utilization amount that limits utilization of the at least one resource by the first logic portion as the first logic portion processes the workload;

monitoring the utilization of the at least one resource by the first logic portion as the workload is processed; and

reporting the utilization of the at least one resource.

28. The method of claim 27 , further comprising:

determining whether the utilization of the at least one resource satisfies the first resource utilization amount;

wherein reporting the utilization comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.

29. The method of claim 27 , further comprising:

receiving an adjustment to the first resource utilization amount; and

applying the adjustment to the first resource utilization amount to determine a second resource utilization amount associated with the at least one resource, and a second resource utilization amount reserved for use by the first logic portion to process the workload.

30. The method of claim 27 , wherein receiving the workload comprises receiving a designation of a logic portion to process the workload.

31. The method of claim 27 , wherein receiving the workload comprises receiving a bit stream indicative of the workload to be processed.

32. The method of claim 27 , wherein the first resource utilization amount is based on an amount of processing throughput reserved for use by the first logic portion.

33. The method of claim 27 , further comprising:

identifying a second resource utilization amount associated with the at least one resource reserved, and a second resource utilization amount reserved for use by a second logic portion from among the plurality of logic portions to process a second workload; and

identifying a limit to the second resource utilization amount that limits utilization of the at least one resource by the second logic portion as the second logic portion processes the second workload.

34. The method of claim 27 , further comprising:

receiving, by the accelerator device, a second workload to be processed by a first logic portion of a second plurality of logic portions of a second ASIC of the accelerator device, the second plurality of logic portions capable of processing respective workloads;

identifying a second resource utilization amount associated with at least one second resource of the accelerator device, and a second resource utilization amount reserved for use by the first logic portion to process the second workload; and

identifying a limit to the second resource utilization amount that limits utilization of the at least one resource by the second logic portion as the second logic portion processes the second workload.

35. The method of claim 27 , wherein the accelerator device is located on a server included in a data center.

36. A system comprising:

a central processing unit;

a memory for use by the central processing unit to execute one or more applications; and

an accelerator device, wherein the accelerator device includes:

an application specific integrated circuit (ASIC) that includes multiple logic portions, wherein the multiple logic portions are configurable to use at least one resource to process respective workloads; and

circuitry to;

identify a first resource utilization amount associated with at least one resource of the accelerator device, and a first resource utilization amount reserved for use by a first logic portion to process a workload,

identify a limit to the first resource utilization amount that limits utilization of the at least one resource by the first logic portion as the first logic portion processes the workload,

monitor the utilization of the at least one resource by the first logic portion as the workload is processed, and

report the utilization of the at least one resource.

37. The system of claim 36 , wherein the accelerator device further includes:

a second ASIC that includes second multiple logic portions, wherein the second multiple logic portions are configurable to use at least one second resource to process respective workloads; and

the circuitry to;

identify a second resource utilization amount associated with the at least one second resource, and a second resource utilization amount reserved for use by a first logic portion from among the multiple second logic portions to process a second workload, and

identify a limit to the second resource utilization amount that limits utilization of the at least one resource by the second logic portion as the second logic portion processes the second workload.

38. The system of claim 36 , wherein the system is included in a data center.

39. An accelerator device comprising:

means for receiving a workload to be processed by a first logic portion of a plurality of logic portions of an application specific integrated circuit (ASIC) of the accelerator device, the plurality of logic portions capable of processing respective workloads;

means for identifying a first resource utilization amount associated with at least one resource of the accelerator device, and a first resource utilization amount reserved for use by the first logic portion to process the workload;

means for identifying a limit to the first resource utilization amount that limits utilization of the at least one resource by the first logic portion as the first logic portion processes the workload;

means for monitoring the utilization of the at least one resource by the first logic portion as the workload is processed; and

means for reporting the utilization of the at least one resource.

40. The accelerator device of claim 39 , further comprising:

means for determining whether the utilization of the at least one resource satisfies the first resource utilization amount;

wherein reporting the utilization comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.

41. The accelerator device of claim 39 , further comprising:

means for receiving an adjustment to the first resource utilization amount; and

means for applying the adjustment to the first resource utilization amount to determine a second resource utilization amount associated with the at least one resource, an a second resource utilization amount reserved for use by the first logic portion to process the workload.

Continuity (7)
Continuation 17733086 · Apr 29, 2022
Continuation 17235135 · Apr 20, 2021
Continuation 15638855 · Jun 30, 2017
Provisional Application 62427268 · Nov 29, 2016
Provisional Application 62376859 · Aug 18, 2016
Provisional Application 62365969 · Jul 22, 2016
Related Publication 20240113954A1 · Apr 4, 2024
References Cited (22)
US 6085295A · Ekanadham et al. · 2000 [cited by applicant]
US 8762916B1 · Kathail et al. · 2014 [cited by applicant]
US 8812765B2 · Dai et al. · 2014 [cited by applicant]
US 8990351B2 · Isaksson · 2015 [cited by applicant]
US 9253055B2 · Nelke et al. · 2016 [cited by applicant]
US 10461774B2 · Balle et al. · 2019 [cited by applicant]
US 10616668B2 · Balle et al. · 2020 [cited by applicant]
US 20030028594A1 · Laschkewitsch et al. · 2003 [cited by applicant]
US 20060059492A1 · Fellenstein et al. · 2006 [cited by applicant]
US 20080229318A1 · Franke · 2008 [cited by applicant]
US 20110296231A1 · Dake · 2011 [cited by applicant]
US 20120233488A1 · Burchard et al. · 2012 [cited by applicant]
US 20140047272A1 · Breternitz et al. · 2014 [cited by applicant]
US 20140047341A1 · Breternitz et al. · 2014 [cited by applicant]
US 20150033134A1 · Bragstad et al. · 2015 [cited by applicant]
US 20150381426A1 · Roese et al. · 2015 [cited by applicant]
US 20160306677A1 · Hira et al. · 2016 [cited by applicant]
US 20170220499A1 · Gray · 2017 [cited by applicant]
CN 105979007A · 2016 [cited by applicant]
Advisory Action for U.S. Appl. No. 15/638, 855, Mailed Nov. 14, 2020, 4 pages. [cited by applicant]
Final Office Action for U.S. Appl. No. 15/638,855, Mailed Jul. 29, 2020, 29 pages. [cited by applicant]
Office Action for U.S. Appl. No. 15/638,855, Mailed Mar. 9, 2020, 28 pages. [cited by applicant]