Dynamic loading neural network inference at DRAM/on-bus SRAM/serial flash for power optimization
Aspects of the disclosure provide a method and an apparatus for executing a program, e.g., a neural network (NN) inference. For example, the apparatus can include an executor and a dynamic loading agent. The executor can be coupled to a second memory, and be configured to execute a portion of the NN inference loaded on the second memory from a first memory that stores the NN inference, and to generate a signal based on a progress of the execution of the NN inference. The dynamic loading agent can be coupled to the executor, the first memory and the second memory, and be configured to load a next portion of the NN inference stored in the first memory to the second memory and to manage power supplied to the first memory based on the signal from the executor and an inference executing scheme stored in the second memory.
1. An apparatus for executing a program, comprising:
an executor that is configured to execute a portion of the program loaded on a second memory from a first memory that stores the program and to generate a signal based on a progress of the execution of the program; and
a dynamic loading agent coupled to the executor, the first memory, and the second memory, the dynamic loading agent being configured to load a next portion of the program stored in the first memory to the second memory and to manage power supplied to the first memory based on the signal from the executor and an executing scheme stored in the second memory.
2. The apparatus of claim 1 , wherein the dynamic loading agent manages the power supplied to the first memory by powering on/off the first memory, configuring an operation mode of the first memory, or scaling a voltage and/or a frequency applied to the first memory.
3. The apparatus of claim 1 , wherein the executing scheme includes a script, a rule, or a model.
4. The apparatus of claim 3 , wherein the rule generates a script for a certain layer of the program based on input tensors from a previous layer of the program.
5. The apparatus of claim 1 , wherein the signal includes an operation, a node identification (ID), a tensor, a kernel, and/or time of the program.
6. The apparatus of claim 1 , wherein the second memory is a tightly-coupled memory (TCM) or a static random access memory (SRAM).
7. The apparatus of claim 1 , wherein the first memory is a dynamic random access memory (DRAM), an on-bus SRAM, or a serial flash memory.
8. The apparatus of claim 1 , wherein:
the executor is a central processing unit (CPU) and the dynamic loading agent is a microcontroller unit (MCU) or a CPU exception, or the executor is a deep learning accelerator (DLA) and the dynamic loading agent is an MCU.
9. The apparatus of claim 1 , wherein the dynamic loading agent and the executor are included on a single chip.
10. The apparatus of claim 1 , further comprising a direct memory access (DMA) controller coupled to the dynamic loading agent, the first memory, and the second memory, wherein the dynamic loading agent is further configured to instruct the DMA controller to load the next portion of the program stored in the first memory to the second memory.
11. The apparatus of claim 1 , wherein the executing scheme is man-made or created by an offline optimizer or an online/runtime optimizer.
12. A method for executing a program, comprising:
loading a portion of the program from a first memory that stores the program to a second memory;
executing the portion of the program loaded on the second memory, and generating a signal based on a progress of the execution of the program; and
loading a next portion of the program stored in the first memory to the second memory and managing power supplied to the first memory based on the signal and an executing scheme stored in the second memory.
13. The method of claim 12 , wherein managing the power supplied to the first memory includes powering on/off the first memory, configuring an operation mode of the first memory, or scaling a voltage and/or a frequency applied to the first memory.
14. The method of claim 12 , wherein the executing scheme includes a script, a rule, or a model.
15. The method of claim 14 , wherein the rule generates a script for a certain layer of the program based on input tensors from a previous layer of the program.
16. The method of claim 12 , wherein the signal includes an operation, a node ID, a tensor, a kernel and/or time of the program.
17. The method of claim 12 , wherein the second memory is a TCM or an SRAM.
18. The method of claim 12 , wherein the first memory is a DRAM, an on-bus SRAM, or a serial flash memory.
19. The method of claim 12 , wherein the executing scheme is man-made or created by an offline optimizer or an online/runtime optimizer.
20. The method of claim 12 , wherein executing the portion of the program and loading a next portion of the program stored in the first memory to the second memory and managing power supplied to the first memory are performed asynchronously.
21. The method of claim 12 , wherein the second memory is more power efficient than the first memory.
22. The apparatus of claim 1 , wherein the second memory is more power efficient than the first memory.