Integrated circuit that extracts data, neural network processor including the integrated circuit, and neural network device
An integrated circuit included in a device for performing a neural network operation includes a buffer configured to store feature map data in units of cells each including at least one feature, wherein the feature map data is for use in the neural network operation; and a multiplexing circuit configured to receive the feature map data from the buffer, and output extracted data by extracting feature data of one of features that are included within a plurality of cells in the received feature map data, the features each corresponding to an identical coordinate value.
1. A neural network processor configured to perform a neural network operation, the neural network processor comprising:
an internal memory configured to receive external data from outside the neural network processor and store data and/or a weight based on the external data;
a data extraction circuit configured to receive data from the internal memory,
store the received data as feature map data in units of cells, each of the cells including matrix-shaped data,
classify features included in the feature map data into a plurality of groups, and
output extracted data by extracting feature data of one feature from each of the plurality of groups, wherein each of the plurality of groups comprises features included in a plurality of cells included in the feature map data, the features each corresponding to an identical coordinate value; and
an arithmetic circuit configured to perform the neural network operation by using the extracted data provided by the data extraction circuit,
wherein the neural network operation includes multiplying the extracted data by the weight provided by the internal memory,
wherein the arithmetic circuit is further configured to perform a convolution operation on the feature map data, the convolution operation including the multiplying the extracted data by the weight provided by the internal memory.
2. The neural network processor of claim 1 , wherein the data extraction circuit comprises:
a buffer configured to store the received data as the feature map data in units of cells; and
a multiplexing circuit configured to output the extracted data by extracting data necessary for the neural network operation from the feature map data received from the buffer.
3. The neural network processor of claim 2 , wherein the multiplexing circuit comprises a first multiplexing circuit comprising a plurality of multiplexers corresponding to the plurality of groups, respectively, each of the plurality of multiplexers being configured to extract feature data of one feature from each of the plurality of groups.
4. The neural network processor of claim 3 , wherein
the first multiplexing circuit is configured to output first data based on pieces of feature data extracted by the plurality of multiplexers, and
the multiplexing circuit further comprises a second multiplexing circuit configured to generate the extracted data by rearranging the first data received from the first multiplexing circuit in at least one of a horizontal direction or a vertical direction.
5. The neural network processor of claim 3 , wherein
the first multiplexing circuit is configured to output first data based on pieces of feature data extracted by the plurality of multiplexers, and
the multiplexing circuit further comprises:
a vertical rotation circuit configured to change an order of rows of the first data in a matrix form and comprising multiplexers, a number of which corresponds to the number of the rows of the first data; and
a horizontal rotation circuit configured to change an order of columns of the first data and comprising multiplexers, a number of which corresponds to the number of the columns of the first data.
6. The neural network processor of claim 3 , wherein the multiplexing circuit rotates the extracted feature data in a vertical direction by changing an order of rows of the extracted feature data in a matrix form, or rotates the extracted feature data in a horizontal direction by changing an order of columns of the extracted feature data.
7. The neural network processor of claim 4 , wherein the second multiplexing circuit comprises:
a horizontal rotation circuit configured to rotate the first data in the horizontal direction by changing an order of columns of the first data in a matrix form, and generate horizontally rotated first data; and
a vertical rotation circuit configured to rotate the horizontally rotated first data in the vertical direction by changing an order of rows of the horizontally rotated first data, and generate the extracted data.
8. The neural network processor of claim 4 , wherein the multiplexing circuit further comprises a data selection circuit configured to remove data unnecessary for the neural network operation from the first data generated by the first multiplexing circuit or the first data rotated by the second multiplexing circuit, when a data window size necessary for the neural network operation is less than a size of each cell.
9. The neural network processor of claim 1 , further comprising an extraction controller configured to provide a control signal such that a multiplexing circuit extracts the extracted data from the feature map data.
10. The neural network processor of claim 1 , wherein a size of the extracted data is equal to or less than a size of the cells.