Apparatus, memory device, and method for multi-phase clock training
Provided are an apparatus, a memory device, and a method for multi-phase clock training. The memory device includes a clock training circuit configured to receive a clock through a first signal pin, among a plurality of signal pins and connected to a first signal line connected to the first signal pin. The clock training circuit generates a multi-phase clock upon receiving the clock, and generates a three-dimensional (3-D) duty offset code (DOC) for the multi-phase clock by simultaneously phase-sweeping between three internal clock signals in a duty adjustment step in the multi-phase clock. The memory device corrects a duty error of the multi-phase clock using the 3-D DOC.
1. A memory device, comprising:
a plurality of signal pins; and
a clock training circuit configured to receive a clock through a first signal pin, among the plurality of signal pins, and connected to a first signal line connected to the first signal pin,
wherein the clock training circuit is further configured to generate a multi-phase clock upon receiving the clock, and generate a three-dimensional duty offset code (3-D DOC) for the multi-phase clock by simultaneously phase-sweeping between three internal clock signals in a duty adjustment step in the multi-phase clock,
wherein the clock training circuit is further configured to perform a first step operation of sweeping phases between the three internal clock signals in a first adjustment range, select a first phase offset point, among phase offset points associated with the first step operation, and output an internal clock signal including the first phase offset point, as a first internal clock signal, and
wherein the first adjustment range includes an adjustment at range of −n to +n steps, wherein n is a non-zero whole number.
2. The memory device as claimed in claim 1 , wherein the clock training circuit is configured to perform a first duty adjustment point evaluation of merging a pulse width window of each of the internal clock signals appearing at the phase offset points associated with the first step operation, and select a phase offset point having a largest value, among merged pulse width windows by the first duty adjustment point evaluation, as the first phase offset point.
3. The memory device as claimed in claim 1 , wherein:
the clock training circuit is configured to perform a second step operation of sweeping the phases between the three internal clock signals in a second adjustment range, based on the first phase offset point as the origin, select a second phase offset point, among phase offset points associated with the second step operation, and output the first internal clock signal including the second phase offset point, as a second internal clock signal, and
the second adjustment range includes an adjustment range of −n/2 to +n/2 steps, wherein n/2 is a non-zero whole number.
4. The memory device as claimed in claim 3 , wherein the clock training circuit is configured to perform a duty adjustment point evaluation of merging a pulse width of each of the three internal clock signals appearing at the phase offset points associated with the second step operation, and select a phase offset point having a largest value, among merged pulse width windows by the duty adjustment point evaluation, as the second phase offset point.
5. The memory device as claimed in claim 4 , wherein the clock training circuit is configured to omit the duty adjustment point evaluation for a phase offset point deviating from the −n/2 to +n/2 steps, among the phase offset points associated with the second step operation.
6. The memory device as claimed in claim 3 , wherein:
the clock training circuit is configured to perform a third step operation of sweeping the phases between the three internal clock signals in a third adjustment range based on the second phase offset point as the origin, select a third phase offset point, among phase offset points associated with the third step operation, and output the second internal clock signal including the third phase offset point, as a third internal clock signal, and
the third adjustment range includes an adjustment range of −n/4 to +n/4 steps, wherein n/4 is a non-zero whole number.
7. The memory device as claimed in claim 6 , wherein the clock training circuit is configured to perform a third duty adjustment point evaluation of merging a pulse width of each of the second internal clock signals appearing at the phase offset points associated with the third step operation, and select a phase offset point having a largest value, among merged pulse width windows by the third duty adjustment point evaluation, as the third phase offset point.
8. The memory device as claimed in claim 7 , wherein the clock training circuit is configured to omit the third duty adjustment point evaluation for a phase offset point deviating from the −n/4 to +n/4 steps, among the phase offset points associated with the third step operation.
9. The memory device as claimed in claim 6 , wherein the clock training circuit is configured to output the third phase offset point as the 3-D DOC.
10. A memory controller, comprising:
a plurality of signal pins; and
a training circuit configured to transmit a clock through a first signal pin, among the plurality of signal pins, receive a three-dimensional duty offset code (3-D DOC) related to the clock through a second signal pin, and connected to a first signal line connected to the first signal pin and a second signal line connected to the second signal pin, wherein:
the training circuit adjusts a timing of the clock based on the 3-D DOC and outputs the adjusted timing to the first signal pin, and
the 3-D DOC is obtained by simultaneously phase-sweeping three internal clock signals in a multi-phase clock derived from the clock in a duty adjustment step by a clock training operation performed in a memory device connected to the first and second signal pins, and is configured to correct a duty error of the multi-phase clock.
11. The memory controller as claimed in claim 10 , wherein:
the clock training operation includes performing a first step operation of sweeping phases between the internal clock signals in a first adjustment range, selecting a first phase offset point, among phase offset points associated with the first step operation, and outputting she an internal clock signal including the first phase offset point, as a first internal clock signal, and
the first adjustment range includes an adjustment range of −n to +n steps, wherein n is a non-zero whole number.
12. The memory controller as claimed in claim 11 , wherein the clock training operation includes performing a first duty adjustment point evaluation of merging a pulse width of each of the internal clock signals appearing at the phase offset points associated with the first step operation, and selecting a phase offset point having a largest value, among merged pulse width windows by the first duty adjustment point evaluation, as the first phase offset point.
13. The memory controller as claimed in claim 11 , wherein:
the clock training operation includes performing a second step operation of sweeping the phases between the internal clock signals in a second adjustment range, based on the first phase offset point as the origin, selecting a second phase offset point, among phase offset points associated with the second step operation, and outputting the first internal clock signal including the second phase offset point, as a second internal clock signal, and
the second adjustment range includes an adjustment range of −n/2 to +n/2 steps, wherein n/2 is a non-zero whole number.
14. The memory controller as claimed in claim 13 , wherein the clock training operation includes performing a duty adjustment point evaluation of merging a pulse width of each of the internal clock signals appearing at the phase offset points associated with the second step operation, and selecting a phase offset point having a largest value, among merged pulse width windows by the duty adjustment point evaluation, as the second phase offset point.
15. The memory controller as claimed in claim 14 , wherein the clock training operation includes omitting the duty adjustment point evaluation for a phase offset point deviating from the −n/2 to +n/2 steps, among the phase offset points associated with the second step operation.
16. The memory controller as claimed in claim 13 , wherein:
the clock training operation includes performing a third step operation of sweeping the phases between the internal clock signals in a third adjustment range, based on the second phase offset point as the origin, selecting a third phase offset point, among phase offset points associated with the third step operation, and outputting the second internal clock signal including the third phase offset point, as a third internal clock signal, and
the third adjustment range includes an adjustment range of −n/4 to +n/4 steps, wherein n/4 is a non-zero whole number.
17. The memory controller as claimed in claim 16 , wherein the clock training operation includes performing a third duty adjustment point evaluation of merging a pulse width of each of the second internal clock signals appearing at the phase offset points associated with the third step operation, and selecting a phase offset point having a largest value, among merged pulse width windows by the third duty adjustment point evaluation, as the third phase offset point.
18. The memory controller as claimed in claim 17 , wherein the clock training operation includes omitting the third duty adjustment point evaluation for a phase offset point deviating from the −n/4 to +n/4 steps, among the phase offset points associated with the third step operation.
19. The memory controller as claimed in claim 16 , wherein the clock training operation includes outputting the third phase offset point as the 3-D DOC.