Apparatuses including Finfets having different gate oxide configurations, and related computing systems
Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.
1. An apparatus, comprising:
first fin field effect transistors (FinFETs) including a first gate oxide material, a second gate oxide material, and a third gate oxide material;
second FinFETs including the second gate oxide material and the third gate oxide material, the second FinFETs substantially free of the first gate oxide material; and
third FinFETs including the third gate oxide material and substantially free of the first gate oxide material and the second gate oxide material, a first fin height of the first FinFETs less than a second fin height of the second FinFETs and a third fin height of the third FinFETs.
2. The apparatus of claim 1 , wherein the first gate oxide material is an in-situ steam generated (ISSG) oxide material.
3. The apparatus of claim 1 , wherein the second gate oxide material is an atomic layer deposition (ALD) oxide material.
4. The apparatus of claim 1 , wherein the third gate oxide material includes a high permittivity (high-k) dielectric material.
5. The apparatus of claim 4 , wherein the third gate oxide material of the third FinFETs also includes an interfacial layer (IL) oxide.
6. An apparatus, comprising:
first fin field effect transistors (FinFETs) having a first fin height and including a first gate oxide material, a second gate oxide material, and a third gate oxide material;
second FinFETs having a second fin height and including the second gate oxide material and the third gate oxide material but substantially free of the first gate oxide material, the first fin height of the first FinFETs less than the second fin height of the second FinFETs; and
third FinFETs having a third fin height and including the third gate oxide material but substantially free of the first gate oxide material and the second gate oxide material, the second fin height of the second FinFETs less than the third fin height of the third FinFETs.
7. The apparatus of claim 1 , wherein:
the first FinFETs include a first gate oxide including the first gate oxide material, the second gate oxide material, and the third gate oxide material;
the second FinFETs include a second gate oxide including the second gate oxide material and the third gate oxide material; and
the third FinFETs include a third gate oxide including the third gate oxide material.
8. The apparatus of claim 7 , wherein the first gate oxide is thicker than the second gate oxide and the third gate oxide.
9. The apparatus of claim 7 , wherein the second gate oxide is thicker than the third gate oxide but thinner than the first gate oxide.
10. A computing system, comprising:
first fin field effect transistors (FinFETs) having a first fin height and including a first gate oxide;
second FinFETs having a second fin height and including a second gate oxide thinner than the first gate oxide; and
third FinFETs having a third fin height and including a third gate oxide thinner than the second gate oxide, the first fin height of the first FinFETs less than the second fin height of the second FinFETs and the third fin height of the third FinFETs.
11. The computing system of claim 10 , further comprising a memory device including periphery circuitry, the periphery circuitry including the first FinFETs, the second FinFETs, and the third FinFETs.
12. The computing system of claim 10 , wherein:
the first gate oxide includes an in-situ steam generated (ISSG) oxide material, an atomic layer deposition (ALD) oxide material, and a high-permittivity (high-k) dielectric material;
the second gate oxide includes the ALD oxide material and the high-k dielectric material; and
the third gate oxide includes an interfacial layer (IL) oxide material and the high-k dielectric material.
13. The computing system of claim 10 , wherein the second fin height of the second FinFETs is less than the third fin height of the third FinFETs.