IP Library › Granted Patent US 12,200,381
Granted Patent B2
US 12,200,381 · App. 17/758,080 · Granted Jan 14, 2025

Solid-state imaging device

Inventors: Dai Suzuki (Kanagawa, JP); Masao Tanaka (Kanagawa, JP); Koji Enoki (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N25/75H04N25/44
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Quick Facts
Patent No.
US 12,200,381
App. No.
17/758,080
Granted
Jan 14, 2025
Kind
B2
Abstract

Image deterioration in an image sensor is inhibited. A solid-state imaging device includes: a pixel array that photoelectrically converts received light and contains pixels arranged in a two-dimensionally arrayed manner, the pixels outputting analog signals; a conversion part that converts the analog signals outputted from the pixels to digital data; a coding part that generates one sign bit or a plurality of sign bits as to the digital data; a storage part that stores the digital data and the sign bit or sign bits; a decoding part that decodes the sign bit or sign bits as to the digital data stored in the storage part; a determination part that determines, on the basis of the decoded sign bit or sign bits, whether or not an error in writing or reading of the digital data in or from the storage part has occurred; and a signal processing part that processes the digital data read from the storage part on the basis of output of the determination part.

Claims (54)

1. A solid-state imaging device, comprising:

a pixel array configured to photoelectrically convert received light, wherein

the pixel array includes a plurality of pixels arranged in a two-dimensionally arrayed manner, and

the plurality of pixels is configured to output analog signals;

a conversion part configured to convert the analog signals output from the plurality of pixels to digital data;

a coding part configured to generate at least one sign bit that corresponds to the digital data;

a storage part configured to store the digital data and the at least one sign bit;

a decoding part configured to decode the at least one sign bit that corresponds to the digital data stored in the storage part;

a determination part configured to:

determine, based on the decoded at least one sign bit, whether an error in a writing operation or a reading operation of the digital data in or from the storage part has occurred; and

determine whether the error in the writing operation or the reading operation in or from the storage part is correctable; and

a signal processing part configured to:

process the digital data read from the storage part based on an output of the determination part; and

detect a defect in the storage part or the plurality of pixels of the pixel array based on an occurrence of the error and a determination that the error is not correctable.

2. The solid-state imaging device according to claim 1 , wherein

the at least one sign bit is an error correction code.

3. The solid-state imaging device according to claim 1 , wherein

in a case where the error has occurred and a determination that the error is correctable, the signal processing part is further configured to execute error correction based on a basis of the at least one sign bit.

4. The solid-state imaging device according to claim 1 , wherein

in a case where the error has occurred and the determination that the error is not correctable, the signal processing part is further configured to execute correction of the digital data in which the error has been detected.

5. The solid-state imaging device according to claim 1 , wherein the determination part is further configured to:

provide error information for the digital data; and

transmit the digital data to the signal processing part.

6. The solid-state imaging device according to claim 5 , wherein

the error information includes information which determines whether the error has occurred.

7. The solid-state imaging device according to claim 5 , wherein

the error information includes information which determines whether the error is correctable.

8. The solid-state imaging device according to claim 5 , wherein

in a case where an image of a plurality of frames is acquired, the determination part is further configured to:

provide the error information for the digital data that corresponds to the image, wherein the error information is provided between the plurality of frames; and

transmit the digital data to the signal processing part.

9. The solid-state imaging device according to claim 5 , wherein the determination part is further configured to:

provide the error information for each packet that constitutes the digital data; and

transmit the digital data to the signal processing part.

10. The solid-state imaging device according to claim 5 , wherein the determination part is further configured to:

provide the error information for each of pixel values based on at least one pixel of the plurality of pixels that constitutes the digital data; and

transmit the digital data to the signal processing part.

11. The solid-state imaging device according to claim 1 , wherein the decoding part is configured to:

decode the at least one sign bit;

detect the error which is correctable; and

correct the error in the digital data based on the decoded at least one sign and the detected error which is correctable.

12. The solid-state imaging device according to claim 1 , further comprising:

a first substrate that includes at least the pixel array; and

a second substrate that includes at least the storage part.

13. The solid-state imaging device according to claim 12 , wherein

the second substrate further includes the conversion part, the coding part, the decoding part, and the determination part.

14. The solid-state imaging device according to claim 13 , wherein

the second substrate further includes the signal processing part.

15. The solid-state imaging device according to claim 12 , wherein

the first substrate and the second substrate are in a layered manner.

16. The solid-state imaging device according to claim 12 , further comprising

a third substrate that includes at least the signal processing part.

17. The solid-state imaging device according to claim 16 , wherein

the first substrate, the second substrate, and the third substrate are in a layered manner.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2022
From: SUZUKI, DAI; TANAKA, MASAO; ENOKI, KOJI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 060593/0020 →
Priority Claims (1)
JP 2020-000489 · Jan 6, 2020 · national
Continuity (1)
Related Publication 20230034032A1 · Feb 2, 2023
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