LED driver for photoplethysmography application and current driver
An LED driver includes an operational amplifier (OP), N current driving circuits, and a resistor circuit. The OP compares a reference voltage with a feedback voltage to generate a control voltage. Each current driving circuit is coupled with an LED, and includes: an NMOS transistor including a drain, a source, and a gate, and being turned on according to the control voltage in an enablement mode and turned off according to the voltage of a ground terminal in a disablement mode, wherein the drain is coupled with the LED and the voltage at the source is the feedback voltage; and a switch circuit coupling the OP with the gate in the enablement mode, and coupling the ground terminal with the gate in the disablement mode. The resistor circuit is coupled between the source and the ground terminal and controls the current passing through the N current driving circuits.
1. A light-emitting diode (LED) driver for a Photoplethysmography (PPG) application, the LED driver comprising:
an operational amplifier (OP) including an OP input end, an OP inverting input end, and an OP output end, wherein the OP input end is for receiving a reference voltage, the OP inverting input end is for receiving a feedback voltage, and the OP output end is for output a control voltage;
N current driving circuit(s), wherein the N is a positive integer, each of the N current driving circuit(s) is coupled with an LED current path, the N current driving circuit(s) is/are coupled with N LED current path(s), and each of the N current driving circuit(s) is configured to operate in one of an enablement mode and a disablement mode and includes:
an n channel metal oxide semiconductor (NMOS) transistor including a drain, a source, and a gate, wherein the drain is coupled with the LED current path via no switch, the source is coupled with the OP inverting input end via a feedback node, the gate is for receiving the control voltage in the enablement mode and for receiving a bias voltage at a bias terminal in the disablement mode, and a voltage at the feedback node is the feedback voltage; and
a switch circuit for coupling the OP output end with the gate in the enablement mode to allow the control voltage to control the NMOS transistor, and the switch circuit further for coupling the bias terminal with the gate in the disablement mode to allow the bias voltage to turn off the NMOS transistor; and
a resistor circuit coupled between the feedback node and a low voltage terminal and configured to determine a total current passing through the N current driving circuit(s) in conjunction with the feedback voltage.
2. The LED driver for the PPG application of claim 1 , wherein regarding each of the N current driving circuit(s), in the disablement mode the NMOS transistor is turned off while the drain of the NMOS transistor is electrically connected with an LED through the LED current path.
3. The LED driver for the PPG application of claim 1 , wherein the N is greater than one, a part of the N current driving circuits operates in the enablement mode, and the other part of the N current driving circuits operates in the disablement mode.
4. The LED driver for the PPG application of claim 1 , wherein regarding each of the N current driving circuit(s), the NMOS transistor has an NMOS circuit area capable of withstanding a maximum NMOS current, the switch circuit includes a first switch and a second switch, the first switch is configured to couple the OP output end with the gate in the enablement mode and the second switch is configured to couple the bias terminal with the gate in the disablement mode, each of the first switch and the second switch has a switch circuit area capable of withstanding a maximum switch current, and the NMOS circuit area is greater than the switch circuit area.
5. The LED driver for the PPG application of claim 1 , wherein both the bias terminal and the low voltage terminal are ground terminals.
6. The LED driver for the PPG application of claim 1 , wherein a total resistance value of the resistor circuit is adjustable.
7. A current driver comprising:
an operational amplifier (OP) including an OP input end, an OP inverting input end, and an OP output end, wherein the OP input end is for receiving a reference voltage, the OP inverting input end is for receiving a feedback voltage, and the OP output end is for output a control voltage;
N current driving circuit(s), wherein the N is a positive integer, each of the N current driving circuit(s) is coupled with a current path and thus the N current driving circuit(s) is/are coupled with N current path(s), and each of the N current driving circuit(s) is configured to operate in one of an enablement mode and a disablement mode and includes:
an NMOS transistor including a drain, a source, and a gate, wherein the drain is coupled with the current path via no switch, the source is coupled with the OP inverting input end via a feedback node, the gate is for receiving the control voltage in the enablement mode and for receiving a bias voltage at a bias terminal in the disablement mode, and a voltage at the feedback node is the feedback voltage; and
a switch circuit for coupling the OP output end with the gate in the enablement mode to allow the control voltage to control the NMOS transistor, and the switch circuit further for coupling the bias terminal with the gate in the disablement mode to allow the bias voltage to turn off the NMOS transistor; and
a resistor circuit coupled between the feedback node and a low voltage terminal and configured to determine a total current passing through the N current driving circuit(s) in conjunction with the feedback voltage.
8. The current driver of claim 7 , wherein regarding each of the N current driving circuit(s), in the disablement mode the NMOS transistor is turned off while the drain of the NMOS transistor is electrically connected with a driven circuit through the current path.
9. The current driver of claim 7 , wherein the N is greater than one, a part of the N current driving circuits operates in the enablement mode, and the other part of the N current driving circuits operates in the disablement mode.
10. The current driver of claim 7 , wherein regarding each of the N current driving circuit(s), the NMOS transistor has an NMOS circuit area capable of withstanding a maximum NMOS current, the switch circuit includes a first switch and a second switch, the first switch is configured to couple the OP output end with the gate in the enablement mode and the second switch is configured to couple the bias terminal with the gate in the disablement mode, each of the first switch and the second switch has a switch circuit area capable of withstanding a maximum switch current, and the NMOS circuit area is greater than the switch circuit area.
11. The current driver of claim 7 , wherein both the bias terminal and the low voltage terminal are ground terminals.
12. The current driver of claim 7 , wherein a total resistance value of the resistor circuit is adjustable.