Method of fabricating semiconductor device having bit line comprising a plurality of pins extending toward the substrate
View Patent ↗The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.
1. A fabricating method of a semiconductor device, comprising:
providing a substrate;
forming a plurality of gate structures in the substrate, each of the gate structures being parallel with each other and extending along a first direction;
forming a plurality of isolation fins on the substrate, each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively; and
forming at least one bit line on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction, wherein the at least one bit line comprises a semiconductor layer, a barrier layer, and a conductive layer stacked from bottom to top and the semiconductor layer and the barrier layer comprise a U-shape structure.
2. The fabricating method of the semiconductor device according to claim 1 , wherein a portion of the isolation fins are formed between the pins of the at least one bit line.
3. The fabricating method of the semiconductor device according to claim 1 , wherein the pins comprise a plurality of first pins and a plurality of second pins, the first pins not directly contact the substrate, the second pins directly contacts the substrate, and the first pins and the second pins are formed through a dual damascene process.
4. The fabricating method of the semiconductor device according to claim 1 , further comprising:
forming a first spacer structure on sidewalls of the at least one bit line; and
forming a second spacer on sidewalls of the isolation fins, wherein the first spacer and the second spacer are simultaneously formed.
5. The fabricating method of the semiconductor device according to claim 4 , wherein the forming of the first spacer and the second spacer is before the forming of the at least one bit line.
6. The fabricating method of the semiconductor device according to claim 4 , wherein a portion of the second spacer is disposed within the substrate and a bottommost surface of the portion of the second spacer is lower than a top surface of the substrate.
7. A fabricating method of a semiconductor device, comprising:
providing a substrate;
forming a plurality of gate structures in the substrate, each of the gate structures being parallel with each other and extending along a first direction;
forming a plurality of isolation fins on the substrate, each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively;
forming at least one bit line on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction; and
forming a first spacer structure on sidewalls of the at least one bit line; and
forming a second spacer on sidewalls of the isolation fins, wherein the first spacer and the second spacer are simultaneously formed, and a portion of the second spacer is disposed within the substrate and a bottommost surface of the portion of the second spacer is lower than a top surface of the substrate.