Systems and methods for multi-phase clock generation
View Patent ↗Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
1. A clock generator comprising:
a phase error corrector configured to receive intermediate signals and to generate N clock output signals, wherein a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees and the phase error corrector is further configured to receive a feedback signal and to reduce phase errors among the clock output signals based on the feedback signal, wherein the phase error corrector includes a phase corrector transistor having a gate terminal configured to receive one of the intermediate signals.
2. The clock generator of claim 1 , further comprising a phase error detector configured to operate in a plurality of modes and each mode detects a phase error between two of the clock output signals and updates the feedback signal based on the detected phase error.
3. The clock generator of claim 2 , wherein a first mode compares a phase of a first clock output signal to a phase of a second clock output signal and adjusts the feedback signal in a first direction if a phase difference between the first clock output signal and the second clock output signal is less than 360/N degrees and adjusts the feedback signal in a second direction if greater than 360/N degrees.
4. The clock generator of claim 3 , wherein:
N=4 and 360/N=90;
a second mode compares a phase of the second clock output signal to a phase of a third clock output signal and adjusts the feedback signal in the first direction if a phase difference between the second clock output signal and the third clock output signal is less than 90 degrees and adjusts the feedback signal in the second direction if greater than 90 degrees;
a third mode compares a phase of the third clock output signal to a phase of a fourth clock output signal and adjusts the feedback signal in the first direction if a phase difference between the third clock output signal and the fourth clock output signal is less than 90 degrees and adjusts the feedback signal in the second direction if greater than 90 degrees; and
a fourth mode compares a phase of the fourth clock output signal to a phase of the first clock output signal and adjusts the feedback signal in the first direction if a phase difference between the fourth clock output signal and the first clock output signal is less than 90 degrees and adjusts the feedback signal in the second direction if greater than 90 degrees.
5. The clock generator of claim 1 , further comprising a phase error detector including a multiplexer configured to select two of the clock output signals based upon a current mode.
6. The clock generator of claim 5 , wherein the phase error detector further includes:
an XOR gate configured to process the two selected clock output signals;
a low pass filter configured to receive an output of the XOR gate;
a slicer configured to process an output of the low pass filter; and
a finite state machine configured to receive an output of the slicer and to adjust the feedback signal based on the received output of the slicer.
7. The clock generator of claim 1 , wherein the feedback signal is a digital signal that is decoded by a digital-to-analog converter to provide a phase shift signal that is applied by the phase error corrector to the intermediate signals to reduce the phase errors among the clock output signals.
8. The clock generator of claim 7 , wherein a first bit of the digital signal represents a direction of phase shift and a second bit and a third bit of the digital signal represent a magnitude of phase shift, the second bit representing a magnitude twice a magnitude of the third bit.
9. The clock generator of claim 1 , wherein the phase corrector transistor has a first source/drain terminal configured to output one of the clock output signals.
10. The clock generator of claim 9 , wherein the phase error corrector further includes a digital-to-analog converter configured to convert the feedback signal into a control voltage that is used to tune a pull down strength of the phase corrector transistor.
11. The clock generator of claim 10 , wherein the phase error corrector further includes a comparison transistor having a first source/drain terminal connected to a second source/drain terminal of the phase corrector transistor, a second source/drain terminal connected to an electrical ground, and a gate terminal configured to receive the control voltage.
12. The clock generator of claim 1 , wherein the phase error corrector further comprises a phase interpolator.
13. A method comprising:
performing phase error correction, by a phase error corrector, based on N intermediate signals to generate N clock output signals, wherein performing the phase error correction reduces phase errors among the clock output signals using a feedback signal received by the phase error corrector; and
adjusting the feedback signal in a first direction if a phase difference between a first clock output signal and a second clock output signal is less than 360/N degrees and adjusting the feedback signal in a second direction if greater than 360/N degrees.
14. The method of claim 13 , further comprising generating the feedback signal by cycling through N modes of phase detection operation and each mode of phase detection operation detects a phase error between two of the clock output signals and updates the feedback signal based on the detected phase error.
15. The method of claim 14 , wherein a first mode compares a phase of a first clock output signal to a phase of a second clock output signal and adjusts the feedback signal in a first direction if a phase difference between the first clock output signal and the second clock output signal is less than 360/N degrees and adjusts the feedback signal in a second direction if greater than 360/N degrees.
16. A quadrature clock generator comprising:
a phase error corrector configured to receive four intermediate signals and to generate four clock output signals, wherein a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 90 degrees and the phase error corrector is further configured to receive a feedback signal and to reduce phase errors among the clock output signals based on the feedback signal; and
a multiplexer configured to select two of the clock output signals based upon a current mode.
17. The quadrature clock generator of claim 16 , wherein the phase error corrector includes a phase corrector transistor having a gate terminal configured to receive one of the intermediate signals and a first source/drain terminal configured to output one of the clock output signals.
18. The quadrature clock generator of claim 17 , wherein the phase error corrector further includes a digital-to-analog converter configured to convert the feedback signal into a control voltage that is used to tune a pull down strength of the phase corrector transistor.
19. The quadrature clock generator of claim 18 , wherein the phase error corrector further includes a comparison transistor having a first source/drain terminal connected to a second source/drain terminal of the phase corrector transistor, a second source/drain terminal connected to an electrical ground, and a gate terminal configured to receive the control voltage.
20. The quadrature clock generator of claim 16 , further comprising a phase error detector including:
the multiplexer;
an XOR gate configured to process the two selected clock output signals;
a low pass filter configured to receive an output of the XOR gate;
a slicer configured to process an output of the low pass filter; and
a finite state machine configured to receive an output of the slicer and to adjust the feedback signal based on the received output of the slicer.