Using a hardware sequencer in a direct memory access system of a system on a chip
In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.
1. An autonomous or semi-autonomous machine that comprises at least one system-on-a-chip (SoC), the at least one SoC comprising a direct memory access (DMA) system that comprises processing circuitry to:
sequence retrieval, from a source, of tiles of a frame according a frame structure associated with the frame; and
write data corresponding to the tiles to a destination memory.
2. The autonomous or semi-autonomous machine of claim 1 , wherein the sequence of the retrieval based at least on a tile structure associated with the frame.
3. The autonomous or semi-autonomous machine of claim 2 , wherein:
the frame structure includes a description identifier; and
the tile structure is retrieved based at least on a descriptor associated with the tile structure corresponding to the description identifier.
4. The autonomous or semi-autonomous machine of claim 1 , wherein:
the frame structure associated with the frame is retrieved by at least receiving a structure that includes:
a tile structure associated with the frame, the tile structure indicating one or more descriptors associated with one or more frames; and
the frame structure associated with the frame, the frame structure indicating
at least one of one or more row descriptors or one or more column descriptors; and
the tiles of the frame are retrieved from the source based at least on the structure.
5. The autonomous or semi-autonomous machine of claim 1 , wherein the processing circuitry is further to determine, based at least on the frame structure, the sequence for retrieving the tiles of the frame.
6. The autonomous or semi-autonomous machine of claim 1 , wherein the source includes at least one of a source memory or a sequencing component.
7. The autonomous or semi-autonomous machine of claim 1 , wherein the processing circuitry is further to, based at least on the data corresponding to the tiles being written to the destination memory, cause a processor to process the data corresponding to the tiles in the destination memory.
8. The autonomous or semi-autonomous machine of claim 1 , wherein the processing circuitry is further to receive, from a processor, an indication that processing associated with the data corresponding to the tiles is complete.
9. A method comprising:
receiving, using a sequence controller, a tile structure associated with a frame;
receiving, using the sequence controller and from a source memory, and based at least on the tile structure, one or more tiles of the frame;
providing, using the sequence controller and to a direct memory access (DMA) engine, the one or more tiles of the frame; and
writing, using the DMA engine, data corresponding to the one or more tiles to a destination memory.
10. The method of claim 9 , further comprising:
receiving a frame structure associated with the frame,
wherein the receiving of the one or more tiles from the source memory is further based at least on the frame structure.
11. The method of claim 10 , wherein:
the frame structure includes a description identifier; and
the receiving the tile structure is based at least on a descriptor associated with the tile structure corresponding to the description identifier.
12. The method of claim 9 , wherein:
the receiving the tile structure associated with the frame comprises receiving, using the sequence controller, a structure that includes:
the tile structure associated with the frame, the tile structure indicating one or more descriptors associated with one or more frames; and
a frame structure associated with the frame, the frame structure indicating
at least one of one or more row descriptors or one or more column descriptors; and
the receiving the one or more tiles from the source memory is based at least on the structure.
13. The method of claim 9 , further comprising:
determining, based at least on the tile structure, a sequence for receiving the one or more tiles of the frame,
wherein the receiving the one or more tiles of the frame from the source memory is based at least on the sequence.
14. The method of claim 9 , further comprising, based at least on the data corresponding to the one or more tiles being written to the destination memory, causing a processor to process the data corresponding to the one or more tiles in the destination memory.
15. The method of claim 9 , further comprising:
receiving, from a processor, an indication that processing associated with the data corresponding to the one or more tiles is complete; and
based at least on the receiving the indication, writing second data corresponding to one or more second tiles of one or more second frames to the destination memory.
16. A direct memory access (DMA) system comprising:
a sequence controller to receive, based at least on a sequence defined in a frame structure corresponding to a frame, one or more tiles of the frame from a source memory; and
a DMA engine to:
receive the one or more tiles of the frame from the sequence controller; and
write data corresponding to the one or more tiles to a destination memory.
17. The DMA system of claim 16 , wherein the data being written to the destination memory causes a processor to process the data.
18. The DMA system of claim 16 , wherein the DMA system is comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a perception system for an autonomous or semi-autonomous machine;
a system for performing simulation operations;
a system for performing deep learning operations;
a system on chip (SoC);
a system including a programmable vision accelerator (PVA);
a system including a vison processing unit;
a system implemented using an edge device;
a system implemented using a robot;
a system incorporating one or more virtual machines (VMs);
a system implemented at least partially in a data center; or
a system implemented at least partially using cloud computing resources.
19. The DMA system of claim 16 , wherein the frame structure indicating at least one of one or more row descriptors or one or more column descriptors.
20. The DMA system of claim 16 , wherein the sequence controller is further to:
receive a tile structure associated with the frame, the tile structure indicating one or more descriptors associated with one or more frames,
wherein the one or more tiles are further received based at least on the tile structure.