Granted Patent B2

US 12,204,824 · App. 17/138,914 · Granted Jan 21, 2025

Inventors: Shushan Wen (Pleasant Hill, CA); Linna Mai (San Jose, CA)

Assignee: Fortinet, Inc.

G06F30/20G06F8/37G06F9/547

Abstract

Claims (33)

1. A design verification test system comprising a compiler (CPL) plugin to, in a network processor, execute a CPL-related design verification test, while maintaining dual compiler support of design verification (DV) and resource packaging (RP), the CPL plugin comprising:

a testcase (TC) to, responsive to a new DV test, read configuration settings and select appropriate plugin processes based on the configuration settings;

an API interface, to generate images that control the special-purpose processor during a stage of a plurality of stages for the new DV test and call the selected plugin processes;

a common compiler module comprising a common function codebase with top-level APIs;

a DV specialized support module comprising a DV function only codebase, wherein the DV has access to the common compiler module; and

an RP specialized support module comprising an RP function only codebase, wherein the RP function only codebase is common for both DV and RP, and wherein the top-level APIs are designed for both DV and RP,

wherein, responsive to completing the new DV test, the TC disables the selected plugin processes and injects traffic for the DV test, and wherein TC reports testing results.

2. The CPL plugin of claim 1 , wherein the special-purpose processor is disposed within a network device.

3. The CPL plugin of claim 1 , wherein at least a portion of the compiler is implemented in microcode.

4. The CPL plugin of claim 1 , wherein the design verification test system interoperates with a specialized driver for networking.

5. The CPL plugin of claim 1 , wherein the design verification test system comprises a system on a chip (SOC).

6. The CPL plugin of claim 1 , wherein the special-purpose processor comprises an ASIC for networking.

7. A method in a special-purpose processor, for executing a compiler (CPL)-related design verification (DV) test, while maintaining dual compiler support of DV and resource packaging (RP), the method comprising the steps of:

detecting a new DV test;

responsive to the new DV test, reading configuration settings to a TC and selecting appropriate plugin processes based on the configuration settings;

generating images that control the special purpose processor, by an API interface, during a stage of a plurality of stages for a CPL-related DV test and call selected plugin processes;

wherein, a common compiler module comprises a common function codebase, a DV specialized support module comprises a DV function only codebase, wherein the DV has access to the common compiler module; an (RP) specialized support module comprises an RP function only codebase, wherein the codebase is common for both DV and RP, and wherein top-level APIs are designed for both DV and RP, and

responsive to completing the DV test, disabling the plugins, injecting traffic and reporting results for the DV test, by the TC, and

responsive to completing the DV test, disabling the plugins, injecting traffic and reporting results for the DV test, by the TC.

8. A non-transitory computer-readable media for, when executed by a special-purpose processor, for executing a CPL-related design verification (DV) test, while maintaining dual compiler support of design verification and resource packaging, the method comprising the steps of:

detecting a new DV test;

responsive to the new DV test, reading configuration settings to a TC and selecting appropriate plugin processes based on the configuration settings;

generating images that control the special purpose processor, by an API interface, during a stage of a plurality of stages for a CPL-related DV test and call selected plugin processes;

wherein, a common compiler module comprises a common function codebase, a DV specialized support module comprises a DV function only codebase, wherein the DV has access to the common compiler module; a resource packaging (RP) specialized support module comprises an RP function only codebase, wherein the codebase is common for both DV and RP, and wherein top-level APIs are designed for both DV and RP, and

responsive to completing the DV test, disabling the plugins, injecting traffic and reporting results for the DV test, by the TC, and

responsive to completing the DV test, disabling the plugins, injecting traffic and reporting results for the DV test, by the TC.

9. The CPL plugin of claim 1 , wherein a TP comprises a TP object which provides information needed by TC, and a TP pointer which is a variable to provide an address for the CPL plugin to find the TP object.

10. The CPL plugin of claim 1 , wherein the TC engages the TP with a call to TP enable and disengages the TP with a call to TC disable.

11. The CPL plugin of claim 1 , wherein the CPL plugin maintains only one codebase for DV and RP.

12. The CPL plugin of claim 1 , wherein APIs of the CPL plugin are designed for both DV and RP.

13. The CPL plugin of claim 1 , wherein functions carrying out workload only for DV should be maintained in a DV database and not in a CPL database.

14. The CPL plugin of claim 1 , wherein functions carrying out workload only for RP should stay in an RP database and not in a CPL database.

15. The CPL plugin of claim 1 , wherein the DV taps into the CPL plugin without breaking up CPL functionality or requiring CPL rebuild.

Assignments (1)

Continuity (1)

References Cited (29)