Memory cell and method of operating the same

1. A memory cell, comprising:

a memory circuit configured to store a first value of a first signal of a first storage node;

a multiplier circuit coupled to the memory circuit, the multiplier circuit being configured to generate an output signal in response to the first signal and a second signal, the output signal corresponding to a product of the first signal and the second signal, the multiplier circuit including:

an output node configured to output the output signal;

a first transistor coupled to the output node and the memory circuit, and being configured to receive at least the second signal; and

an initialization circuit coupled to the first transistor by the output node, and being configured to initialize the multiplier circuit in response to at least a third signal or a fourth signal.

2. The memory cell of claim 1 , wherein the initialization circuit configured to initialize the multiplier circuit comprises:

the initialization circuit being further configured to set the output signal during an initialization phase of the memory circuit in response to at least the third signal or the fourth signal.

3. The memory cell of claim 2 , wherein the initialization circuit comprises:

a second transistor of a first type, the second transistor comprising:

a first source/drain terminal coupled to the output node and the first transistor;

a second source/drain terminal coupled to a reference voltage supply, the reference voltage supply having a reference voltage corresponding to the third signal; and

a first gate terminal configured to receive the fourth signal.

4. The memory cell of claim 1 , wherein the first transistor is further configured to set the output signal, during a sensing phase of the memory circuit, in response to at least the second signal.

5. The memory cell of claim 4 , wherein the first transistor is a P-type transistor, and the first transistor comprises:

a first source/drain terminal coupled to the output node and the initialization circuit;

a second source/drain terminal configured to receive the second signal; and

a first gate terminal coupled to a second storage node of the memory circuit, and being configured to receive a fifth signal from the memory circuit, the fifth signal corresponding to a voltage of the second storage node.

6. The memory cell of claim 5 , wherein the fifth signal is inverted from the first signal.

7. The memory cell of claim 4 , wherein the first transistor is an N-type transistor, and the first transistor comprises:

a first source/drain terminal coupled to the output node and the initialization circuit;

a second source/drain terminal configured to receive the second signal; and

a first gate terminal coupled to the first storage node of the memory circuit, and being configured to receive the first signal from the memory circuit, the first signal corresponding to a voltage of the first storage node.

8. The memory cell of claim 1 , wherein the memory cell corresponds to an 8-transistor (8T) static random access (SRAM) cell.

9. The memory cell of claim 1 , wherein the memory circuit comprises:

a first bit line;

a second bit line;

a first word line;

a first cross-coupled inverter;

a second cross-coupled inverter coupled to the first cross-coupled inverter;

a first pass-gate transistor coupled to the first bit line, the first word line and the first cross-coupled inverter; and

a second pass-gate transistor coupled to the second bit line, the first word line and the second cross-coupled inverter.

10. A memory cell array, comprising:

a first set of memory circuits configured to store weight data, the first set of memory circuits including:

a first memory circuit configured to store a first weight value of a first signal of a first storage node;

a first set of multiplier circuits configured to perform computing-in memory (CIM) operations between the weight data and input data, the first set of multiplier circuits including:

a first multiplier circuit coupled to the first memory circuit, the first multiplier circuit being configured to generate an output signal in response to the first signal and a second signal, the output signal corresponding to a CIM product operation between the first signal and the second signal, the first multiplier circuit including:

a first output node configured to output the output signal;

a first transistor coupled to the first output node and the first memory circuit, and being configured to receive at least the second signal; and

an initialization circuit coupled to the first transistor by the first output node, and being configured to initialize the first multiplier circuit in response to at least a third signal or a fourth signal,

wherein each multiplier circuit of the first set of multiplier circuits corresponds to each memory circuit of the first set of memory circuits.

11. The memory cell array of claim 10 , wherein the CIM product operation between the first signal and the second signal corresponds to an AND operation between the first signal and the second signal.

12. The memory cell array of claim 10 , wherein the first transistor is further configured to set the output signal, during a sensing phase of the first memory circuit, in response to at least the second signal.

13. The memory cell array of claim 12 , wherein the first transistor is an N-type transistor, and the first transistor comprises:

a first source/drain terminal coupled to the first output node and the initialization circuit;

a second source/drain terminal configured to receive the second signal; and

a first gate terminal coupled to the first storage node of the first memory circuit, and being configured to receive the first signal from the first memory circuit, the first signal corresponding to a voltage of the first storage node.

14. The memory cell array of claim 12 , wherein the first transistor is a P-type transistor, and the first transistor comprises:

a first source/drain terminal coupled to the first output node and the initialization circuit;

a second source/drain terminal configured to receive the second signal; and

a first gate terminal coupled to a second storage node of the first memory circuit, and being configured to receive a fifth signal from the first memory circuit, the fifth signal corresponding to a voltage of the second storage node,

wherein the fifth signal is inverted from the first signal.

15. The memory cell array of claim 10 , wherein the initialization circuit configured to initialize the first multiplier circuit comprises:

the initialization circuit being further configured to set the output signal during an initialization phase of the first memory circuit in response to at least the third signal or the fourth signal.

16. The memory cell array of claim 15 , wherein the initialization circuit comprises:

a second transistor of a first type, the second transistor comprising:

a first source/drain terminal coupled to the first output node and the first transistor;

a second source/drain terminal coupled to a reference voltage supply, the reference voltage supply having a reference voltage corresponding to the third signal; and

a first gate terminal configured to receive the fourth signal.

17. The memory cell array of claim 10 , wherein the memory cell array corresponds to an array of 8-transistor (8T) static random access (SRAM) cells.

18. A method of operating a memory cell, the method comprising:

performing a write operation of the memory cell, the memory cell including a memory circuit and a multiplier circuit, the performing the write operation of the memory cell comprising:

storing a first value of a first signal in a first storage node of the memory circuit, the first signal corresponding to a first weight;

performing, by the multiplier circuit, a computing-in memory (CIM) operation between the first signal and a second signal, the multiplier circuit including a first transistor and an initialization circuit, wherein performing the CIM operation between the first signal and the second signal comprises:

initializing, by the initialization circuit, an output signal of the multiplier circuit in response to at least a third signal or a fourth signal; and

setting, by the first transistor, the output signal, during a sensing phase of the memory circuit, in response to at least the second signal.

19. The method of claim 18 , wherein initializing the output signal of the multiplier circuit comprises:

setting the second signal to an initialization value during an initialization phase of the memory circuit, the initialization circuit including a second transistor;

turning on the second transistor in response to the third signal, thereby electrically coupling a first node of the multiplier circuit to an output node of the multiplier circuit; and

setting a value of the output signal to be equal to a value of the fourth signal.

20. The method of claim 19 , wherein setting the output signal, during the sensing phase of the memory circuit, comprises:

turning off the second transistor in response to the third signal, thereby electrically decoupling the first node and the output node from each other;

setting the second signal to a non-initialization value during the sensing phase of the memory circuit; and

setting the value of the output signal in response to turning on or off the first transistor.