IP Library › Granted Patent US 12,205,659
Granted Patent B2
US 12,205,659 · App. 18/483,448 · Granted Jan 21, 2025

Iterative programming of analog content addressable memory

Inventors: Giacomo Pedretti (Verbania, IT); John Paul Strachan (San Carlos, CA); Catherine Graves (Milpitas, CA)
Assignee: Hewlett Packard Enterprise Development LP
G11C27/005G11C15/046
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Quick Facts
Patent No.
US 12,205,659
App. No.
18/483,448
Granted
Jan 21, 2025
Kind
B2
Abstract

Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.

Claims (13)

1. A circuit for efficiently implementing the programming method in hardware comprising:

an analog content addressable memory (aCAM) array;

a digital-to-analog converter (DAC) circuit block;

a pre charge circuit block (PC);

a programming circuit block (PM);

a sense amplifier circuit block (SA);

an AND gate; and

a digital signal processing (DSP) unit controlling the circuit.

2. The circuit of claim 1 , wherein the DAC circuit block receives a digital input and returns an analog output for a data line (DL) voltage and a voltage of the SA (V sense ).

3. The circuit of claim 1 , wherein the PC receives a clock value and returns a charge to a match line (ML) when the clock value is high.

4. The circuit of claim 1 , wherein the PM is a memristor conductance programming circuit block that executes an algorithm when triggered.

5. The circuit of claim 1 , wherein the SA returns a high value if the voltage on match line (ML) is higher than an output from the DAC circuit block.

6. The circuit of claim 1 , wherein the DSP unit controlling the circuit receives an End Of Programming (EOP) bit from the AND gate and stops the process based on the EOP bit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2023
From: PEDRETTI, GIACOMO; STRACHAN, JOHN PAUL; GRAVES, CATHERINE
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 065163/0497 →
Continuity (2)
Continuation 17514847 · Oct 29, 2021
Related Publication 20240047002A1 · Feb 8, 2024
References Cited (8)
US 9646695B2 · Chiou et al. · 2017 [cited by applicant]
US 9721661B1 · Buchanan et al. · 2017 [cited by applicant]
US 9847132B1 · Zheng et al. · 2017 [cited by applicant]
US 10847238B2 · Li et al. · 2020 [cited by applicant]
US 10998047B1 · Li et al. · 2021 [cited by applicant]
US 11551771B2 · Strachan et al. · 2023 [cited by applicant]
US 11561607B2 · Graves et al. · 2023 [cited by applicant]
US 11783907B2 · Pedretti · 2023 [cited by examiner]