Guard region for an integrated circuit
An integrated circuit includes a first semiconductor device with an N type region biased by a first terminal and a second semiconductor device with a second region. An N type guard region is located laterally between the N type region of the first semiconductor device and the second region. A P type region is isolated in the N type guard region and is biased by a second terminal. The N type guard region is either electrically coupled to the second terminal through a resistor circuit or is characterized as floating.
1. An integrated circuit comprising:
a first semiconductor device including an N type region in a substrate of the integrated circuit, the N type region is configured to be biased by a first integrated circuit terminal;
a second semiconductor device including a second region located in the substrate;
an N type guard region located in the substrate and including a portion located laterally between the N type region and the second region;
a P type guard region isolated in the N type guard region, the P type guard region is configured to be biased by a second integrated circuit terminal;
wherein the N type guard region is either electrically coupled to the second integrated circuit terminal through a resistive circuit or is characterized as floating.
2. The integrated circuit of claim 1 wherein the N type guard region is electrically coupled to the second integrated circuit terminal through the resistive circuit.
3. The integrated circuit of claim 2 wherein the resistive circuit is characterized as a polysilicon resistor.
4. The integrated circuit of claim 2 wherein the resistive circuit includes a current path located in a doped semiconductor region of the substrate.
5. The integrated circuit of claim 2 wherein the resistive circuit includes a transistor whose control terminal is configured to be biased to provide a resistance between its current terminals.
6. The integrated circuit of claim 2 wherein the resistive circuit is configured to provide a resistance in a range of 0.1 kilo ohm to 10 kilo ohms.
7. The integrated circuit of claim 1 wherein the N type guard region is characterized floating.
8. The integrated circuit of claim 1 wherein the integrated circuit is configured that during a condition when a voltage of the first integrated circuit terminal is below a voltage of the second integrated circuit terminal by at least a first voltage difference, at least a portion of the N type guard region located adjacent to the P type guard region is at a lower voltage than the P type guard region.
9. The integrated circuit of claim 1 wherein the N type guard region is characterized as having a ring configuration and laterally surrounds the N type region, wherein the second region is located laterally outside of the N type guard region.
10. The integrated circuit of claim 9 wherein the P type guard region is characterized as having a ring configuration and laterally surrounds the N type region.
11. The integrated circuit of claim 1 wherein the first semiconductor device is characterized as an NFET device, wherein the N type region is characterized as a drain region of the NFET device.
12. The integrated circuit of claim 1 wherein the first semiconductor device is characterized as a power transistor for a DC-DC power converter.
13. The integrated circuit of claim 1 wherein:
the integrated circuit is configured that during a condition when a voltage of the first integrated circuit terminal is below a voltage of the second integrated circuit terminal by at least a first voltage difference, a parasitic NPN transistor in the substrate becomes conductive and a parasitic PNP transistor in the substrate becomes conductive to provide a path for current from the second integrated circuit terminal to the first integrated circuit terminal;
for the parasitic NPN transistor, the N type region is characterized as an emitter, a P type region of the substrate is characterized as a base, and the N type guard region is characterized as a collector;
for the parasitic PNP transistor, the P type guard region is characterized as an emitter, the N type guard region is characterized as a base, and the P type region is characterized as a collector.
14. The integrated circuit of claim 1 comprising:
a buried N type region located directly below the first semiconductor device and in contact with the N type guard region.
15. The integrated circuit of claim 1 wherein the second integrated circuit terminal is characterized as a ground terminal.
16. An integrated circuit comprising:
a semiconductor device including an N type region in a substrate of the integrated circuit, the N type region is configured to be biased by a first integrated circuit terminal;
an N type guard region located in the substrate and laterally surrounding the N type region;
a P type guard region isolated in the N type guard region, the P type guard region is configured to be biased by a second integrated circuit terminal;
wherein the N type guard region is either electrically coupled to the second integrated circuit terminal through a resistive circuit or is characterized as floating.
17. The integrated circuit of claim 16 wherein the N type guard region is electrically coupled to the second integrated circuit terminal through the resistive circuit.
18. The integrated circuit of claim 16 wherein the N type guard region is characterized floating.
19. The integrated circuit of claim 16 wherein the P type guard region laterally surrounds the N type region.
20. The integrated circuit of claim 16 comprising:
a buried N type region located directly below the first semiconductor device and in contact with the N type guard region.