IP Library › Granted Patent US 12,206,430
Granted Patent B2
US 12,206,430 · App. 18/022,071 · Granted Jan 21, 2025

A/D converter

Inventor: Koji Obata (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H03M1/46
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Quick Facts
Patent No.
US 12,206,430
App. No.
18/022,071
Granted
Jan 21, 2025
Kind
B2
Abstract

A comparator compares a differential voltage between a voltage to be converted as an analog input voltage and a comparative voltage generated by a D/A converting unit with a comparison reference voltage. A switching circuit selectively connects a capacitor, associated with the analog input voltage selected as the voltage to be converted, to an output terminal of an integrator. The integrator integrates the differential voltage in a state where an A/D converting section has performed conversion operation on a least significant bit. A comparison reference voltage generating unit uses, as the comparison reference voltage, a charge voltage for the capacitor associated with the analog input voltage selected as the voltage to be converted.

Claims (65)

1. An A/D converter comprising:

an input switching circuit configured to receive a plurality of analog input voltages and output, as a voltage to be converted, one analog input voltage selected from the plurality of analog input voltages; and

an A/D converting section configured to perform A/D conversion of converting the voltage to be converted, supplied from the input switching circuit, into a multi-bit digital signal, the A/D converting section being a successive approximation register A/D converting section,

the input switching circuit being configured to, when a conversion operation of converting the voltage to be converted has been performed by the A/D converting section, select another analog input voltage, as the voltage to be converted, from the plurality of analog input voltages,

the A/D converting section being configured to perform the conversion operation on a target bit basis from a most significant bit through a least significant bit,

the A/D converting section including:

a control unit;

a D/A converting unit configured to generate an analog comparative voltage, corresponding to the target bit, in accordance with a control signal supplied from the control unit;

a comparison reference voltage generating unit configured to generate a comparison reference voltage corresponding to the analog input voltage selected as the voltage to be converted; and

a comparator configured to determine a value of the target bit by comparing a differential voltage between the voltage to be converted and the comparative voltage with the comparison reference voltage,

the control unit being configured to determine, based on a result of comparison made by the comparator with respect to the target bit, the control signal with respect to a bit next to the target bit,

the comparison reference voltage generating unit including:

an integrator configured to integrate the differential voltage in a state where the A/D converting section has performed the conversion operation on the least significant bit;

a plurality of capacitors provided in association with the plurality of analog input voltages, respectively; and

a switching circuit configured to selectively connect a capacitor, associated with the analog input voltage selected as the voltage to be converted, out of the plurality of capacitors to an output terminal of the integrator,

the capacitor, connected to the output terminal of the integrator via the switching circuit, out of the plurality of capacitors being charged with an output voltage of the integrator,

the comparison reference voltage generating unit being configured to use, as the comparison reference voltage, a charge voltage for the capacitor, associated with the analog input voltage selected as the voltage to be converted, out of the plurality of capacitors.

2. The A/D converter of claim 1 , wherein

each of the plurality of capacitors has one terminal thereof connected to a reference voltage for the A/D converter, and

the switching circuit includes a plurality of switches respectively connected between the other terminals of the plurality of capacitors and the output terminal of the integrator.

3. The A/D converter of claim 2 , wherein

each of the plurality of capacitors has capacitance which is at least 100 times as large as a quantity of electric charge that leaks via an associated one of the switches during a holding period until one analog input voltage, associated with the capacitor, out of the plurality of analog input voltages is A/D converted next time.

4. The A/D converter of claim 1 , comprising a filter circuit configured to attenuate an RF component of the digital signal supplied from the A/D converting section, wherein

the filter circuit includes:

a plurality of filters respectively associated with the plurality of analog input voltages; and

a filter switching circuit configured to supply the digital signal to one filter, associated with the analog input voltage selected as the voltage to be converted, out of the plurality of filters.

5. The A/D converter of claim 1 , wherein

the D/A converting unit includes:

a plurality of capacitors, each of the plurality of capacitors having one terminal thereof connected to an output terminal of the input switching circuit; and

a voltage switching circuit configured to selectively connect, in accordance with the control signal, the other terminal of each of the plurality of capacitors to either a first voltage or a second voltage.

6. The A/D converter of claim 1 , wherein

the integrator includes multiple stages of integrating circuits configured to perform integration operations sequentially, and

each of the multiple stages of the integrating circuits performs the integration operation using an operational amplifier.

7. The A/D converter of claim 2 , comprising a filter circuit configured to attenuate an RF component of the digital signal supplied from the A/D converting section, wherein

the filter circuit includes:

a plurality of filters respectively associated with the plurality of analog input voltages; and

a filter switching circuit configured to supply the digital signal to one filter, associated with the analog input voltage selected as the voltage to be converted, out of the plurality of filters.

8. The A/D converter of claim 3 , comprising a filter circuit configured to attenuate an RF component of the digital signal supplied from the A/D converting section, wherein

the filter circuit includes:

a plurality of filters respectively associated with the plurality of analog input voltages; and

a filter switching circuit configured to supply the digital signal to one filter, associated with the analog input voltage selected as the voltage to be converted, out of the plurality of filters.

9. The A/D converter of claim 2 , wherein

the D/A converting unit includes:

a plurality of capacitors, each of the plurality of capacitors having one terminal thereof connected to an output terminal of the input switching circuit; and

a voltage switching circuit configured to selectively connect, in accordance with the control signal, the other terminal of each of the plurality of capacitors to either a first voltage or a second voltage.

10. The A/D converter of claim 3 , wherein

the D/A converting unit includes:

a plurality of capacitors, each of the plurality of capacitors having one terminal thereof connected to an output terminal of the input switching circuit; and

a voltage switching circuit configured to selectively connect, in accordance with the control signal, the other terminal of each of the plurality of capacitors to either a first voltage or a second voltage.

11. The A/D converter of claim 4 , wherein

the D/A converting unit includes:

a plurality of capacitors, each of the plurality of capacitors having one terminal thereof connected to an output terminal of the input switching circuit; and

a voltage switching circuit configured to selectively connect, in accordance with the control signal, the other terminal of each of the plurality of capacitors to either a first voltage or a second voltage.

12. The A/D converter of claim 2 , wherein

the integrator includes multiple stages of integrating circuits configured to perform integration operations sequentially, and

each of the multiple stages of the integrating circuits performs the integration operation using an operational amplifier.

13. The A/D converter of claim 3 , wherein

the integrator includes multiple stages of integrating circuits configured to perform integration operations sequentially, and

each of the multiple stages of the integrating circuits performs the integration operation using an operational amplifier.

14. The A/D converter of claim 4 , wherein

the integrator includes multiple stages of integrating circuits configured to perform integration operations sequentially, and

each of the multiple stages of the integrating circuits performs the integration operation using an operational amplifier.

15. The A/D converter of claim 5 , wherein

the integrator includes multiple stages of integrating circuits configured to perform integration operations sequentially, and

each of the multiple stages of the integrating circuits performs the integration operation using an operational amplifier.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2023
From: OBATA, KOJI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 064411/0161 →
Priority Claims (1)
JP 2020-145080 · Aug 28, 2020 · national
Continuity (1)
Related Publication 20230370083A1 · Nov 16, 2023
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