Wireline receiver sampling circuit
Embodiments included herein are directed towards sampling circuits and methods of using the same. Embodiments may include a data sense amplifier circuit and a reference sense amplifier circuit directly connected with the data sense amplifier circuit. Embodiments may further include a latch circuit configured to receive a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit. The latch circuit may be further configured to generate a least significant bit output based upon, at least in part, the first input and the second input.
1. A sampling circuit comprising:
a data sense amplifier circuit;
a reference sense amplifier circuit directly connected with the data sense amplifier circuit; and
a latch circuit configured to receive a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit, the latch circuit further configured to generate a least significant bit output based upon, at least in part, the first input and the second input.
2. The sampling circuit of claim 1 , wherein the data sense amplifier circuit and the reference sense amplifier circuit compete to discharge their respective output voltages.
3. The sampling circuit of claim 1 , wherein the latch circuit is a set/reset (SR) latch circuit.
4. The sampling circuit of claim 1 , wherein an absolute value of a differential input is compared to a threshold value to generate the least significant bit output.
5. The sampling circuit of claim 1 , wherein the data sense amplifier circuit and the reference sense amplifier circuit include a differential pair of transistors.
6. A sampling method comprising:
providing a data sense amplifier circuit and a reference sense amplifier circuit electrically connected with the data sense amplifier circuit;
receiving a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit at a latch circuit; and
generating a least significant bit output based upon, at least in part, the first input and the second input.
7. The sampling method of claim 6 , further comprising:
comparing a respective output voltage of the data sense amplifier circuit and the reference sense amplifier circuit.
8. The sampling method of claim 6 , wherein the latch circuit is a set/reset (SR) latch circuit.
9. The sampling method of claim 6 , further comprising:
comparing an absolute value of a differential input to a threshold value to generate the least significant bit output.
10. The sampling method of claim 6 , wherein the data sense amplifier circuit and the reference sense amplifier circuit include a differential pair of transistors.
11. A pulse amplitude modulation 4-level (PAM4) sampling circuit comprising:
a data sense amplifier circuit;
a reference sense amplifier circuit; and
a latch circuit configured to receive a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit, the latch circuit further configured to generate a least significant bit output based upon, at least in part, the first input and the second input.
12. The sampling circuit of claim 11 , wherein the data sense amplifier circuit and the reference sense amplifier circuit compete to discharge their respective output voltages.
13. The sampling circuit of claim 11 , wherein the latch circuit is a set/reset (SR) latch circuit.
14. The sampling circuit of claim 11 , wherein an absolute value of a differential input is compared to a threshold value to generate the least significant bit output.
15. The sampling circuit of claim 11 , wherein the data sense amplifier circuit and the reference sense amplifier circuit include a differential pair of transistors.
16. A pulse amplitude modulation 4-level (PAM4) sampling method comprising:
providing a data sense amplifier circuit and a reference sense amplifier circuit;
receiving a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit at a latch circuit; and
generating a least significant bit output based upon, at least in part, the first input and the second input.
17. The sampling method of claim 16 , further comprising:
comparing a respective output voltage of the data sense amplifier circuit and the reference sense amplifier circuit.
18. The sampling method of claim 16 , wherein the latch circuit is an SR latch circuit.
19. The sampling method of claim 16 , further comprising:
comparing an absolute value of a differential input to a threshold value to generate the least significant bit output.
20. The sampling method of claim 16 , wherein the data sense amplifier circuit and the reference sense amplifier circuit include a differential pair of transistors that each include three regions of operation during a transition from a reset state to a data settling state.