Receiver circuit and method
A receiver circuit includes an equalizer configured to process a received signal; a first offset circuit configured to apply a first offset voltage to the processed signal, the first offset voltage having a first polarity; a second offset circuit configured to apply a second offset voltage to the processed signal, the second offset voltage having a second polarity opposite to the first polarity; a first amplification circuit configured to amplify a first output signal provided by the first offset circuit; a second amplification circuit configured to amplify a second output signal provided by the second offset circuit; and a third amplification circuit configured to amplify the processed signal.
1 . A receiver circuit comprising:
an equalizer configured to process a received signal;
a first offset circuit configured to apply a first offset voltage to the processed signal, the first offset voltage having a first polarity;
a second offset circuit configured to apply a second offset voltage to the processed signal, the second offset voltage having a second polarity opposite to the first polarity;
a first amplification circuit configured to amplify a first output signal provided by the first offset circuit;
a second amplification circuit configured to amplify a second output signal provided by the second offset circuit;
a third amplification circuit configured to amplify the processed signal;
a first comparison circuit configured to compare an output signal of the first amplification circuit with a threshold voltage and provide a first comparison result;
a second comparison circuit configured to compare an output signal of the second amplification circuit with the threshold voltage and provide a second comparison result; and
a third comparison circuit configured to compare an output signal of the third amplification circuit with the threshold voltage and provide a third comparison result.
2 . The receiver circuit according to claim 1 , wherein
the processed signal includes a plurality of Eyes, each of the Eyes having a different voltage range,
the first offset circuit is configured to apply the first offset voltage to the processed signal, causing a center of an Upper Eye of the processed signal is about 0 V, and
the second offset circuit is configured to apply the second offset voltage to the processed signal, causing a center of a Lower Eye of the processed signal is about 0 V.
3 . The receiver circuit according to claim 1 , wherein
the first to third comparison results are superimposed on each of the first output signal, the second output signal, and the third output signal.
4 . The receiver circuit according to claim 1 , wherein
the first offset circuit and the second offset circuit each include one of a voltage source, a buffer circuit, or both of a capacitor and a resistor.
5 . The receiver circuit according to claim 1 , wherein
when the received signal is a PAM-N signal (N is an integer of 4 or more), (N−1) amplification circuits are provided.
6 . The receiver circuit according to claim 1 , wherein the receiver circuit is operatively integrated into an interface circuit.
7 . A receiver circuit comprising:
an equalizer configured to process a received signal;
a first offset circuit configured to apply a first offset voltage to the processed signal, the first offset voltage having a first polarity;
a second offset circuit configured to apply a second offset voltage to the processed signal, the second offset voltage having a second polarity opposite to the first polarity;
a first amplification circuit configured to amplify a first output signal provided by the first offset circuit;
a second amplification circuit configured to amplify a second output signal provided by the second offset circuit;
a first comparison circuit configured to compare an output signal of the first amplification circuit with a threshold voltage and output a first comparison result;
a second comparison circuit configured to compare an output signal of the second amplification circuit with the threshold voltage and output a second comparison result; and
a third comparison circuit configured to interpolate the output signals of the first and second comparison circuits, compare an interpolation result with the threshold voltage, and output a third comparison result.
8 . The receiver circuit according to claim 7 , wherein
when the received signal is a PAM-N signal (N is an integer of 4 or more), N/2 amplification circuits are provided.
9 . The receiver circuit according to claim 7 , wherein the receiver circuit is operatively integrated into an interface circuit.
10 . The receiver circuit according to claim 8 , wherein the processed signal includes a plurality of Eyes, each of the Eyes having a different voltage range,
the first offset circuit is configured to apply the first offset voltage to the processed signal, causing a center of an Upper Eye of the processed signal is about 0 V, and
the second offset circuit is configured to apply the second offset voltage to the processed signal, causing a center of a Lower Eye of the processed signal is about 0 V.
11 . The receiver circuit according to claim 7 , wherein
the first and second comparison results are superimposed on each of the output signals of the first and second comparison circuits.
12 . The receiver circuit according to claim 7 , wherein
the first offset circuit and the second offset circuit each include one of a voltage source, a buffer circuit, or both of a capacitor and a resistor.
13 . A method of a receiver circuit, comprising:
applying a first offset voltage to a signal processed by an equalizer, the first offset voltage having a first polarity;
applying a second offset voltage to the processed signal, the second offset voltage having a second polarity opposite to the first polarity;
amplifying the processed signal with the first offset as a first output signal;
amplifying the processed signal with the second offset as a second output signal;
amplifying the processed signal without an offset as a third output signal;
comparing the first output signal with a threshold voltage and providing a first comparison result;
comparing the second output signal with the threshold voltage and providing a second comparison result; and
comparing the third output signal with the threshold voltage and providing a third comparison result.
14 . The method according to claim 13 , further comprising:
superimposing the first to third comparison results on each of the first output signal, the second output signal, and the third output signal.
15 . The method according to claim 13 , wherein
each of the first offset circuit and the second offset circuit is applied by one of a voltage source, a buffer circuit, or both of a capacitor and a resistor.
16 . The method according to claim 13 , wherein
the processed signal includes a plurality of Eyes, each of the Eyes having a different voltage range, the method further comprises:
applying the first offset voltage to the processed signal, causing a center of an Upper Eye of the processed signal is about 0 V, and
applying the second offset voltage to the processed signal, causing a center of a Lower Eye of the processed signal is about 0 V.