Interface device for intercom access control systems
This disclosure describes an electronic device that can be installed within an access control system in parallel with a legacy interface device. The electronic device may perform steps of determining a set of configuration settings associated with an access control system to which the electronic device is electrically connected, receiving, by the electronic device, a first signal in a format associated with the access control system, configuring, based on the set of configuration settings, one or more signal pathways within the electronic device, generating, by routing the first signal through the one or more signal pathways, a second signal in a second format, and providing the second signal to at least one second electronic device.
1. An electronic device comprising:
one or more processors;
memory;
a wireless transceiver;
bus transmission circuitry including
a first transistor,
a first input line electrically connected to a third terminal of the first transistor,
a first bus connection line electrically connected to a second terminal of the first transistor,
a second bus connection line electrically connected to a first terminal of the first transistor,
a capacitor,
a second input line electrically connected to the capacitor,
a first switch electrically connected to the capacitor and to the first bus connection line, the first switch being transitionable between a closed state in which the capacitor is electrically connected to the first bus connection line through the first switch, and an open state, and
a third input line electrically connected to the switch.
2. The electronic device of claim 1 , wherein
the first transistor comprises an N-channel metal oxide semiconductor field effect transistor,
the third terminal of the first transistor comprises a gate terminal,
the second terminal of the first transistor comprises a drain terminal,
the first terminal of the first transistor comprises a source terminal,
the capacitor comprises a polarized capacitor, and
the first switch comprises a solid state relay.
3. The electronic device of claim 1 , wherein the first input line is electrically connected to an output terminal of an operational amplifier.
4. The electronic device of claim 1 , wherein the first input line is electrically connected to a comparator.
5. The electronic device of claim 1 , wherein the second input line is electrically connected to a driver, and wherein a fourth input line is electrically connected to the driver.
6. The electronic device of claim 1 , wherein the electronic device comprises a controller.
7. The electronic device of claim 1 , wherein the electronic device comprises
a digital potentiometer;
a fourth input line electrically connected to the digital potentiometer;
a power line electrically connected to the digital potentiometer;
a fifth input line;
an operational amplifier;
wherein the fifth input line is electrically connected to a first input terminal of the operational amplifier;
wherein a connection line connects an output terminal of the digital potentiometer to a second input terminal of the operational amplifier;
wherein the first input line is electrically connected to an output terminal of the operational amplifier.
8. The electronic device of claim 1 , wherein the electronic device comprises bus receiving circuitry including
a fourth input line electrically connected to the first bus connection line,
a coupling relay,
an attenuator,
an amplifier,
a second switch and a third switch, the second switch and the third switch being transitionable together between
a first state in which the fourth input line is electrically connected to the amplifier through the coupling relay, and
a second state in which the fourth input line is electrically connected to the amplifier through the attenuator,
a comparator electrically connected to the amplifier,
a fifth input line electrically connected to the comparator,
one or more amplitude shift keying demodulator components electrically connected to the comparator,
one or more frequency shift keying demodulator components electrically connected to the comparator,
a first output line electrically connected to the comparator
a second output line electrically connected to the one or more amplitude shift keying components; and
a third output line electrically connected to the one or more frequency shift keying components.
9. The electronic device of claim 1 , wherein the electronic device comprises one or more electronically-readable media storing instructions that, when executed by the one or more processors, cause the electronic device to
receive first data using the wireless transceiver,
store, based on the first data, first configuration settings associated with a first model of intercom system,
receive second data using the wireless transceiver,
send, over the first bus connection line, a first signal generated using the first input line and the first transistor based on the second data and the first configuration settings associated with the first model of intercom system,
receive third data using the wireless transceiver,
store, based on the third data, second configuration settings associated with a second model of intercom system,
receive fourth data using the wireless transceiver,
send, over the first bus connection line, a second signal generated using the second input line and the switch based on the fourth data and the second configuration settings associated with the second model of intercom system.
10. An electronic device comprising:
bus transmission circuitry including
a first transistor electrically connected to a first input line, a first bus connection line, and a second bus connection line,
a switch electrically connected to the first bus connection line, and
a second input line electrically connected to the switch, the switch being transitionable between a closed state in which the second input line is electrically connected to the first bus connection line through the first switch, and an open state;
a network interface;
one or more processors; and
one or more electronically-readable media storing instructions that, when executed by the one or more processors, cause the electronic device to
receive first data using the network interface,
store, based on the first data, first configuration settings associated with a first model of intercom system,
receive second data using the network interface,
send, over the first bus connection line, a first signal generated using the first input line and the first transistor based on the second data and the first configuration settings associated with the first model of intercom system,
receive third data using the network interface,
store, based on the third data, second configuration settings associated with a second model of intercom system,
receive fourth data using the network interface,
send, over the first bus connection line, a second signal generated using the second input line and the switch based on the fourth data and the second configuration settings associated with the second model of intercom system.
11. The electronic device of claim 10 , wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to couple a signal from the second input line on top of the first bus connection line.
12. The electronic device of claim 10 , wherein the switch comprises an opto-coupler relay, the opto-coupler relay comprising a light emitting diode and one or more photo sensors.
13. The electronic device of claim 10 , wherein the switch comprises a solid-state relay.
14. The electronic device of claim 10 , wherein the transistor comprises an N-channel metal oxide semiconductor field effect transistor.
15. The electronic device of claim 10 , wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to send over the first bus connection line, in response to receiving the second data using the network interface, the first signal based on
sending a third signal over the first input line, the third signal over the first input line causing the transistor to electrically connect the first bus connection line to the second bus connection line for a first period of time,
sending a fourth signal over the first input line, the fourth signal over the first input line causing the transistor to electrically connect the first bus connection line to the second bus connection line for a second period of time.
16. The electronic device of claim 10 , wherein the electronic device comprises a digital potentiometer, and wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to transmit over the first bus connection line, in response to receiving the second data using the network interface, the first signal based on
sending a third signal over a third input line, the third signal over the third input line causing the digital potentiometer to adjust a resistance of the digital potentiometer to a first resistance value,
transmitting a fourth signal over a fourth input line, the fourth signal over the first input line causing the transistor to electrically connect the first bus connection line to the second bus connection line for a first period of time,
transmitting a fifth signal over the third input line, the fifth signal over the third input line causing the digital potentiometer to adjust a resistance of the digital potentiometer to a second resistance value that is different than the first resistance value, and
transmitting a sixth signal over the fourth input line, the sixth signal over the fourth input line causing the transistor to electrically connect the first bus connection line to the second bus connection line for a second period of time.
17. The electronic device of claim 10 , wherein the electronic device comprises receiving circuitry including a first receiving switch, attenuator circuitry, comparator circuitry, and coupling relay circuitry, and wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to
generate fifth data using the first receiving switch, the attenuator circuitry, and the comparator circuitry based on
a third signal received over the first bus connection line, and
the first configuration settings associated with the first model of intercom access control device.
18. The electronic device of claim 17 , wherein the electronic device comprises receiving circuitry including a first receiving switch, attenuator circuitry, comparator circuitry, and coupling relay circuitry, and wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to
generate fifth data using the first receiving switch, the attenuator circuitry, and the comparator circuitry based on
a third signal received over the first bus connection line, and
the second configuration settings associated with the second model of intercom access control device.
19. The electronic device of claim 18 , wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to
generate sixth data using the first receiving switch, the coupling relay circuitry, and the comparator circuitry based on
a fourth signal received over the first bus connection line, and
the first configuration settings associated with the first model of intercom access control device.
20. The electronic device of claim 17 , wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to
generate sixth data using the first receiving switch, the coupling relay circuitry, and the comparator circuitry based on
a fourth signal received over the first bus connection line, and
the second configuration settings associated with the second model of intercom access control device.
21. The electronic device of claim 10 , wherein the electronic device comprises receiving circuitry including a frequency shift keying (FSK) demodulator component and an amplitude shift keying (ASK) demodulator component.
22. The electronic device of claim 21 , wherein the first configuration settings or the second configuration settings indicate a center frequency for use by the ASK demodulator component.
23. The electronic device of claim 10 , wherein the electronic device comprises a controller.
24. The electronic device of claim 10 , wherein the electronic device comprises inter-integrated circuit lines, and wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to
send, based on the first configuration settings, a third signal over the first input line electrically connected to the transistor, the first input line being one of the inter-integrated circuit lines, and the third signal causing the transistor to electrically connect the first bus connection line to the second bus connection line.
25. The electronic device of claim 10 , wherein the electronic device comprises inter-integrated circuit lines, and wherein the one or more electronically-readable media store instructions that, when executed by the one or more processors, cause the electronic device to
transmit, based on the first configuration settings, a third signal over a third input line electrically connected to a digital potentiometer, the third input line being one of the inter-integrated circuit lines, and the third signal causing the digital potentiometer to adjust a resistance of the digital potentiometer; and
transmit, based on the first configuration settings, a fourth signal over the first input line electrically connected to the transistor, the first input line being one of the inter-integrated circuit lines, and the fourth signal causing the transistor to electrically connect the first bus connection line to the second bus connection line.