Inter-cluster shared data management in sub-NUMA cluster
An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.
1. A system, comprising:
two or more sub-non-uniform memory access clusters (SNCs);
a processor core; and
circuitry communicatively coupled to the two or more SNCs and the processor core, the circuitry to:
allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space.
2. The system of claim 1 , further comprising:
a register to store the indicated SNC memory allocation policy.
3. The system of claim 1 , wherein the circuitry is further to:
determine the indicated SNC memory allocation policy based on an instruction that triggered the request to initialize the specified memory space.
4. The system of claim 1 , wherein the circuitry is further to:
override a default memory allocation policy for the two or more SNCs with the indicated SNC memory allocation policy.
5. The system of claim 1 , wherein the circuitry is further to:
determine if the indicated SNC memory allocation policy indicates that the specified memory space is to be interleaved; and, if so determined,
allocate the specified memory space to be interleaved among all of the two or more SNCs.
6. An apparatus comprising:
decode circuitry to decode a single instruction, the single instruction to include a field for an opcode; and
execution circuitry to execute the decoded instruction according to the opcode to provide an indicated sub-non-uniform memory access cluster (SNC) memory allocation policy.
7. The apparatus of claim 6 , wherein the execution circuitry is further to execute the decoded instruction according to the opcode to:
store information in a register that corresponds to the indicated SNC memory allocation policy.
8. The apparatus of claim 6 , wherein the opcode intrinsically specifies the indicated SNC memory allocation policy.
9. The apparatus of claim 8 , wherein the single instruction further includes a field for an identifier of a source operand and a field for an identifier of a destination operand, and wherein the execution circuitry is further to execute the decoded instruction according to the opcode to:
retrieve source information from a location indicated by the source operand; and
store the source information to a location indicated by the destination operand in accordance with the indicated SNC memory allocation policy.
10. The apparatus of claim 9 , wherein the execution circuitry is further to execute the decoded instruction according to the opcode to:
allocate a memory space specified by the destination operand in two or more SNCs in accordance with the indicated SNC memory allocation policy.
11. The apparatus of claim 10 , wherein the execution circuitry is further to execute the decoded instruction according to the opcode to:
override a default memory allocation policy for the specified memory space of the two or more SNCs with the indicated SNC memory allocation policy.
12. The apparatus of claim 11 , wherein the execution circuitry is further to execute the decoded instruction according to the opcode to:
determine if the indicated SNC memory allocation policy indicates that the specified memory space is to be interleaved; and, if so determined,
allocate the specified memory space to be interleaved among all of the two or more SNCs.
13. The apparatus of claim 12 , wherein the execution circuitry is further to execute the decoded instruction according to the opcode to:
allocate the specified memory space to be interleaved among all of the two or more SNCs at a page granularity.
14. The apparatus of claim 12 , wherein the execution circuitry is further to execute the decoded instruction according to the opcode to:
allocate the specified memory space to be interleaved among all of the two or more SNCs at a block granularity.
15. A method, comprising:
fetching an instruction having a field for an opcode;
decoding the instruction;
scheduling execution of the instruction; and
executing the decoded instruction to provide an indicated sub-non-uniform memory access cluster (SNC) memory allocation policy according to the opcode.
16. The method of claim 15 , wherein the instruction has fields for a destination operand and a source operand, and wherein the opcode intrinsically specifies the indicated SNC memory allocation policy.
17. The method of claim 16 , further comprising:
retrieving source information from a location indicated by the source operand; and
storing the source information to a location indicated by the destination operand in accordance with the indicated SNC memory allocation policy.
18. The method of claim 17 , further comprising:
allocating a memory space specified by the destination operand in two or more SNCs in accordance with the indicated SNC memory allocation policy; and
overriding a default memory allocation policy for the specified memory space of the two or more SNCs with the indicated SNC memory allocation policy.
19. The method of claim 18 , further comprising:
determining if the indicated SNC memory allocation policy indicates that the specified memory space is to be interleaved; and, if so determined,
allocating the specified memory space to be interleaved among all of the two or more SNCs.
20. The method of claim 19 , further comprising:
allocating the specified memory space to be interleaved among all of the two or more SNCs at one of a page granularity and a block granularity.