IP Library › Granted Patent US 12,210,896
Granted Patent B2
US 12,210,896 · App. 18/586,172 · Granted Jan 28, 2025

Frameworks and interfaces for offload device-based packet processing

Inventors: Pradeep Vincent (Kenmore, WA); Matthew David Klein (Seattle, WA); Samuel James McKelvie (Seattle, WA)
Assignee: Amazon Technologies, Inc.
G06F9/45558H04L12/4633H04L41/082H04L45/74H04L63/0272H04L63/20G06F2009/45595
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Quick Facts
Patent No.
US 12,210,896
App. No.
18/586,172
Granted
Jan 28, 2025
Kind
B2
Abstract

A network device can include packet processing circuitry to provide support for virtual functions. The packet processing circuitry can perform operations such as receiving data traffic from a virtual machine, determining an egress rule for the data traffic based on a rule table, and encapsulating the data traffic according to the egress rule.

Claims (25)

1. A peripheral device comprising:

processing circuitry; and

a memory storing instructions that, when executed by the processing circuitry, cause the peripheral device to perform operations including:

receiving data traffic from a virtual machine;

determining an egress rule for the data traffic based on a rule table; and

encapsulating the data traffic according to the egress rule.

2. The peripheral device of claim 1 , wherein the data traffic is received by a virtual function assigned to the virtual machine.

3. The peripheral device of claim 2 , wherein the operations further include verifying that a source media access control (MAC) address of each packet in the data traffic is associated with the virtual machine.

4. The peripheral device of claim 3 , wherein the operations further include verifying that a source internet protocol (IP) address of each packet in the data traffic is associated with the virtual machine.

5. The peripheral device of claim 1 , wherein the operations further include trapping broadcast packets.

6. The peripheral device of claim 1 , wherein the operations further include dropping packets having an invalid source MAC address or an invalid source IP address.

7. The peripheral device of claim 1 , wherein the egress rule is determined by matching a destination MAC address in the rule table.

8. The peripheral device of claim 7 , wherein the egress rule is further determined by matching a destination IP subnet in the rule table.

9. The peripheral device of claim 7 , wherein the egress rule includes inserting an outer source MAC address, an outer destination MAC address, an outer source IP address, and an outer destination IP address to each packet of the data traffic.

10. The peripheral device of claim 9 , wherein the outer source MAC address is a MAC address of the peripheral device.

11. The peripheral device of claim 9 , wherein the egress rule includes prepending an opaque field to each packet of the data traffic.

12. The peripheral device of claim 9 , wherein the egress rule includes replacing the source MAC address and the destination MAC address of each packet of the data traffic.

13. The peripheral device of claim 7 , wherein the egress rule provides a pointer to a memory location storing a tunnel header to prepend to each packet of the data traffic.

14. The peripheral device of claim 13 , wherein the memory location is part of a trusted root memory partition.

15. The peripheral device of claim 7 , wherein the egress rule includes a throttling rate.

16. The peripheral device of claim 15 , wherein the throttling rate is different from one or more other egress rules in the rule table.

17. The peripheral device of claim 1 , wherein the operations include updating metrics associated with the egress rule.

18. The peripheral device of claim 17 , wherein the metrics include number of bytes and number of packets processed according to the egress rule.

19. The peripheral device of claim 1 , wherein the operations include segmenting packets of the data traffic according to a maximum transmission unit size.

20. The peripheral device of claim 19 , wherein the maximum transmission unit size is set by a trusted domain.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2024
From: VINCENT, PRADEEP; KLEIN, MATTHEW DAVID; MCKELVIE, SAMUEL JAMES
To: AMAZON TECHNOLOGIES, INC.
Reel/Frame 066550/0108 →
Continuity (8)
Continuation 18311693 · May 3, 2023
Continuation 17445080 · Aug 13, 2021
Continuation 16789337 · Feb 12, 2020
Continuation 15904236 · Feb 23, 2018
Continuation 14923276 · Oct 26, 2015
Continuation 14321492 · Jul 1, 2014
Continuation 13076347 · Mar 30, 2011
Related Publication 20240248747A1 · Jul 25, 2024
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