Display panel and display device
A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write device, a drive device and a bias adjustment device. The data write device is configured to provide a data signal to the drive device. The bias adjustment device is configured to provide a bias adjustment signal to the drive device. The display panel further includes a drive circuit, the drive circuit is configured to receive a first drive signal and a second drive signal. In a case where the drive device includes a drive transistor being a PMOS transistor, the bias adjustment signal is same as the first drive signal, or, in a case where the drive device includes a drive transistor being an NMOS transistor, and the bias adjustment signal is same as the second drive signal.
1. A display panel, comprising:
a pixel circuit and a light-emitting element;
wherein
the pixel circuit comprises a data write device, a drive device and a bias adjustment device;
the data write device is configured to provide a data signal to the drive device; and
the bias adjustment device is configured to provide a bias adjustment signal to the drive device;
wherein, the display panel further comprises a drive circuit and an integrated chip;
the integrated chip is configured to provide a first drive signal and a second drive signal to the drive circuit; and
the drive circuit is configured to at least receive the first drive signal and the second drive signal, generate a drive signal according to the first drive signal and the second drive signal, and provide the drive signal to the pixel circuit, the first drive signal is a high-level signal, and the second drive signal is a low-level signal;
wherein the display panel comprises a bias adjustment signal line, a first drive signal line and a second drive signal line, the bias adjustment signal line is used to provide the bias adjustment signal to the bias adjustment device, and the first drive signal line and the second drive signal line are respectively disposed at least one side frame of the display panel; and
wherein,
in a case where the drive device comprises a drive transistor being a P-type transistor, the bias adjustment signal is same as the first drive signal, and the bias adjustment signal line is connected to the first drive signal line; or
in a case where the drive device comprise a drive transistor being an N-type transistor, and the bias adjustment signal is same as the second drive signal, and the bias adjustment signal line is connected to the second drive signal line.
2. The display panel according to claim 1 , wherein
the first drive signal line and the second drive signal line are disposed in a same side frame of the display panel; or,
the first drive signal line and the second drive signal line are disposed in different side frames of the display panel.
3. The display panel according to claim 1 , wherein
a working process of the pixel circuit comprises a bias adjustment stage, and in the bias adjustment stage, the bias adjustment device is turned on and is configured to receive the bias adjustment signal.
4. The display panel according to claim 1 , wherein
the data write device is connected to a source of the drive transistor; and
the bias adjustment device is connected between a source of the drive transistor or a drain of the drive transistor and the bias adjustment signal line.
5. The display panel according to claim 1 , wherein
the pixel circuit further comprises a compensation device, and the compensation device is connected between a gate of the drive transistor and a drain of the drive transistor; and,
a working process of the pixel circuit comprises a bias adjustment stage, and in the bias adjustment stage, the bias adjustment device is turned on and the compensation device is turned off.
6. The display panel according to claim 1 , wherein
the pixel circuit further comprises a reset device;
an end of the reset device is connected to a reset signal line and configured to receive a reset signal, and another end of the reset device is connected to a gate of the drive transistor; and
in a reset stage, the reset device is turned on to provide the reset signal to the gate of the drive transistor.
7. The display panel according to claim 6 , wherein
a working process of the pixel circuit comprises a bias adjustment stage, and in the bias adjustment stage, the bias adjustment device is turned on; and
the reset stage at least partially overlap the bias adjustment stage in time.
8. The display panel according to claim 1 , wherein
the pixel circuit further comprises a reset device;
a one end of the reset device is connected to a reset signal line and configured to receive a reset signal, and another end of the reset device is connected to a drain of the drive transistor;
the pixel circuit further comprises a compensation device, the compensation device is connected between a gate of the drive transistor and the drain of the drive transistor; and
in a reset stage, the reset device and the compensation device are turned on to provide the reset signal to the gate of the drive transistor.
9. The display panel according to claim 1 , wherein
the pixel circuit further comprises an initialization device;
an end of the initialization device is connected to an initialization signal line and configured to receive an initialization signal, and another end of the initialization device is connected to the light-emitting element; and
in an initialization stage, the initialization device is turned on to provide the initialization signal to the light-emitting element.
10. The display panel according to claim 9 , wherein
a control terminal of the initialization device and a control terminal of the bias adjustment device are connected to a same scan signal line, and in the initialization stage, the scan signal line is used to control the initialization device and the bias adjustment device to be turned on at a same time.
11. The display panel according to claim 9 , wherein
the pixel circuit further comprises a reset device;
an end of the reset device is connected to a reset signal line and configured to receive a reset signal, another end of the reset device is connected to a gate of the drive transistor, and in a reset stage, the reset device is turned on to provide the reset signal to the gate of the drive transistor, and
a control terminal of the initialization device, a control terminal of the bias adjustment device, and a control terminal of the reset device are all connected to a same scan signal line, and in the initialization stage, the scan signal line is used to control the initialization device, the bias adjustment device, and the reset device to be turned on at a same time.
12. A display device, comprising a display panel,
the display panel, comprising:
a pixel circuit and a light-emitting element;
wherein
the pixel circuit comprises a data write device, a drive device and a bias adjustment device;
the data write device is configured to provide a data signal to the drive device; and
the bias adjustment device is configured to provide a bias adjustment signal to the drive device;
wherein, the display panel further comprises a drive circuit and an integrated chip;
the integrated chip is configured to provide a first drive signal and a second drive signal to the drive circuit; and
the drive circuit is configured to at least receive the first drive signal and the second drive signal, generate a drive signal according to the first drive signal and the second drive signal, and provide the drive signal to the pixel circuit, the first drive signal is a high-level signal, and the second drive signal is a low-level signal;
wherein the display panel comprises a bias adjustment signal line, a first drive signal line and a second drive signal line, the bias adjustment signal line is used to provide the bias adjustment signal to the bias adjustment device, and the first drive signal line and the second drive signal line are respectively disposed at least one side frame of the display panel; and
wherein,
in a case where the drive device comprises a drive transistor being a P-type transistor, the bias adjustment signal is same as the first drive signal, and the bias adjustment signal line is connected to the first drive signal line; or
in a case where the drive device comprise a drive transistor being an N-type transistor, and the bias adjustment signal is same as the second drive signal, and the bias adjustment signal line is connected to the second drive signal line.