IP Library › Granted Patent US 12,211,796
Granted Patent B2
US 12,211,796 · App. 17/355,747 · Granted Jan 28, 2025

Microelectronic assemblies having topside power delivery structures

Inventors: Bernd Waidhas (Pettendorf, DE); Carlton Hanna (Santa Jose, CA); Stephen Morein (San Jose, CA); Lizabeth Keser (San Diego, CA); Georg Seidemann (Landshut, DE)
Assignee: Intel Corporation
H01L23/5384H01L23/50H01L23/5222H01L23/5227H01L23/5385H01L23/5386
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Quick Facts
Patent No.
US 12,211,796
App. No.
17/355,747
Granted
Jan 28, 2025
Kind
B2
Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.

Claims (44)

1. A microelectronic assembly, comprising:

a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source;

a first microelectronic component, having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material on the surface of the package substrate and including a through-substrate via (TSV) electrically coupled to the first conductive pathway;

a second microelectronic component, having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in the insulating material; and

a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

2. The microelectronic assembly of claim 1 , wherein the TSV is a first TSV, and further comprising:

a second TSV in the second microelectronic component electrically coupled to the first conductive pathway in the package substrate and to the second conductive pathway in the RDL.

3. The microelectronic assembly of claim 1 , wherein the insulating material is a first insulating material, and further comprising:

a capacitive element embedded in a second insulating material between the package substrate and the first insulating material and electrically coupled to the first conductive pathway and the TSV.

4. The microelectronic assembly of claim 1 , wherein the RDL has a first surface and an opposing second surface and the insulating material is at the first surface of the RDL, and further comprising:

an inductor at the second surface of the RDL and electrically coupled to the second conductive pathway.

5. The microelectronic assembly of claim 4 , further comprising:

a capacitive element between the inductor and the second surface of the RDL, wherein the capacitive element is electrically coupled to the inductor and to the second conductive pathway.

6. The microelectronic assembly of claim 1 , wherein the surface of the package substrate is a second surface and the package substrate further includes an opposing first surface, and further comprising:

a circuit board electrically coupled to the first surface of the package substrate, wherein the power source is on the circuit board.

7. The microelectronic assembly of claim 6 , further comprising:

a capacitive element at the first surface of the package substrate and electrically coupled to the first conductive pathway.

8. The microelectronic assembly of claim 1 , further comprising:

a heat transfer structure on the RDL.

9. The microelectronic assembly of claim 1 , wherein the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor.

10. The microelectronic assembly of claim 1 , wherein the second microelectronic component is a voltage regulator configured to convert a low current high voltage signal to a low voltage high current signal.

11. A microelectronic assembly, comprising:

a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source;

a first microelectronic component, having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material on the surface of the package substrate;

a second microelectronic component, having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in the insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive pathway; and

a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

12. The microelectronic assembly of claim 11 , wherein the surface of the package substrate is a second surface and the package substrate further includes an opposing first surface, and further comprising:

a circuit board electrically coupled to the first surface of the package substrate, wherein the power source is on the circuit board.

13. The microelectronic assembly of claim 11 , further comprising:

a heat transfer structure at the second surface of the RDL.

14. The microelectronic assembly of claim 11 , wherein the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor.

15. The microelectronic assembly of claim 11 , wherein the second microelectronic component is a voltage regulator.

16. A microelectronic assembly, comprising:

a circuit board including a power source;

a package substrate on the circuit board and including a first conductive pathway electrically coupled to the power source;

an insulating material on the package substrate;

a first microelectronic component, having a first surface at the package substrate and an opposing second surface, embedded in the insulating material and including a first through-substrate via (TSV) electrically coupled to the first conductive pathway;

a second microelectronic component, having a first surface at the package substrate and an opposing second surface, embedded in the insulating material and including a second TSV electrically coupled to the first conductive pathway; and

a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the first and second TSVs, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

17. The microelectronic assembly of claim 16 , wherein the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor.

18. The microelectronic assembly of claim 16 , wherein the second microelectronic component is a voltage regulator.

19. The microelectronic assembly of claim 16 , further comprising:

a third microelectronic component, having a first surface electrically coupled to the package substrate and an opposing second surface, embedded in the insulating material and including a third TSV electrically coupled to the first conductive pathway and the second conductive pathway.

20. The microelectronic assembly of claim 19 , wherein the third microelectronic component is a die including input and output circuitry.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE 4TH INVENTOR'S NAME PREVIOUSLY RECORDED ON REEL 56863 FRAME 316. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 18, 2024
From: WAIDHAS, BERND; HANNA, CARLTON; MOREIN, STEPHEN; KESER, LIZABETH; SEIDEMANN, GEORG
To: INTEL CORPORATION
Reel/Frame 069206/0699 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2021
From: WAIDHAS, BERND; HANNA, CARLTON; MOREIN, STEPHEN; KESER, LIZBETH; SEIDEMANN, GEORG
To: INTEL CORPORATION
Reel/Frame 056863/0316 →
Continuity (1)
Related Publication 20220415806A1 · Dec 29, 2022
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