Memory device having 2-transistor vertical memory cell and conductive shield structure
Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.
1. An apparatus comprising:
a first memory cell including a first transistor and a second transistor, the first transistor including a first channel region and a first charge storage structure separated from the first channel region, and the second transistor including a second channel region formed over the charge storage structure;
a second memory cell adjacent the first memory cell, the second memory cell including a third transistor and a fourth transistor, the third transistor including a third channel region and a second charge storage structure separated from the third channel region, and the fourth transistor including a fourth channel region formed over the second charge storage structure;
a first access line adjacent a side of the first memory cell;
a second access line adjacent a side of the second memory cell;
a first dielectric material adjacent the first channel region;
a second dielectric material adjacent the third channel region; and
a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials, wherein the conductive structure is electrically separated from the first access line.
2. The apparatus of claim 1 , wherein the first channel region and the second channel region have different conductivity types.
3. The apparatus of claim 1 , wherein the second channel region includes semiconducting oxide material.
4. The apparatus of claim 1 , wherein:
each of the first and second access lines and the conductive structure has a height in a direction perpendicular to a direction from the first memory cell to the second memory cell; and
the height of the conductive structure is the same as the height of each of the first and second access lines.
5. The apparatus of claim 1 , wherein:
each of the first and second access lines and the conductive structure has a thickness in a direction parallel to a direction from the first memory cell to the second memory cell; and
the thickness of the conductive structure is the same as the thickness of each of the first and second access lines.
6. The apparatus of claim 1 , wherein:
each of the first and second access lines and the conductive structure has a thickness in a direction parallel to a direction from the first memory cell to the second memory cell; and
the thickness of the conductive structure is greater than the thickness of each of the first and second access lines.
7. The apparatus of claim 1 , wherein the second channel region includes at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In 2 O 3 ), tin oxide (SnO 2 ), titanium oxide (TiOx), zinc oxide nitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indiumzinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).
8. An apparatus comprising:
a first memory cell including a first transistor and a second transistor, the first transistor including a first channel region and a first charge storage structure separated from the first channel region, and the second transistor including a second channel region formed over the charge storage structure;
a second memory cell adjacent the first memory cell, the second memory cell including a third transistor and a fourth transistor, the third transistor including a third channel region and a second charge storage structure separated from the third channel region, and the fourth transistor including a fourth channel region formed over the second charge storage structure;
a first access line adjacent a side of the first memory cell;
a second access line adjacent a side of the second memory cell;
a first dielectric material adjacent the first channel region;
a second dielectric material adjacent the third channel region; and
a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials, wherein:
each of the first and second access lines and the conductive structure has a height in a direction perpendicular to a direction from the first memory cell to the second memory cell; and
the height of the conductive structure is unequal to the height of each of the first and second access lines.
9. An apparatus comprising:
a first trench, a second trench, and a third trench, the second trench being between the first and third trenches;
a first memory cell between the first and second trenches, the first memory cell including a first side and a second side opposite from the first side, a first transistor including a first channel region and a first charge storage structure separated from the first channel region, and a second transistor including a second channel region formed over the charge storage structure;
a second memory cell between the second and third trenches, the second memory cell including a first side and a second side opposite from the first side, a third transistor including a third channel region and a second charge storage structure separated from the third channel region, and a fourth transistor including a fourth channel region formed over the second charge storage structure;
a first access line in the second trench and adjacent the second side of the first memory cell;
a second access line in the second trench and adjacent the first side of the second memory cell;
a first conductive shield structure adjacent the first side of the first memory cell, wherein the first conductive shield is electrically separated from the first access line; and
a second conductive shield structure adjacent the second side of the second memory cell, wherein the second conductive shield is electrically separated from the second access line.
10. The apparatus of claim 9 , wherein the apparatus comprises a memory device having memory cells and access lines for the memory cells, wherein:
the first and second memory cells are included in the memory cells;
the first and second access lines are included in the access lines; and
each of the first and third trenches void of an access line among the access lines.
11. The apparatus of claim 9 , wherein the first, second, and third trenches have a same width in a direction parallel to a direction from the first memory cell to the second memory cell.
12. The apparatus of claim 9 , wherein:
each of the first, second, and third trenches have a width in a direction parallel to a direction from the first memory cell to the second memory cell; and
the width of the second trench is greater than the width of each of the first and third trenches.
13. An apparatus comprising:
a first trench, a second trench, and a third trench, the second trench being between the first and third trenches;
a first memory cell between the first and second trenches, the first memory cell including a first side and a second side opposite from the first side, a first transistor including a first channel region and a first charge storage structure separated from the first channel region, and a second transistor including a second channel region formed over the charge storage structure;
a second memory cell between the second and third trenches, the second memory cell including a first side and a second side opposite from the first side, a third transistor including a third channel region and a second charge storage structure separated from the third channel region, and a fourth transistor including a fourth channel region formed over the second charge storage structure;
a first access line in the second trench and adjacent the second side of the first memory cell;
a second access line in the second trench and adjacent the first side of the second memory cell;
a first conductive shield structure adjacent the first side of the first memory cell; and
a second conductive shield structure adjacent the second side of the second memory cell, wherein:
each of the first and second access lines and the conductive shield structure has a thickness in a direction parallel to a direction from the first memory cell to the second memory cell; and
the thickness of the conductive shield structure is greater than the thickness of each of the first and second access lines.
14. An apparatus comprising:
a first trench, a second trench, and a third trench, the second trench being between the first and third trenches;
a first memory cell between the first and second trenches, the first memory cell including a first side and a second side opposite from the first side, a first transistor including a first channel region and a first charge storage structure separated from the first channel region, and a second transistor including a second channel region formed over the charge storage structure;
a second memory cell between the second and third trenches, the second memory cell including a first side and a second side opposite from the first side, a third transistor including a third channel region and a second charge storage structure separated from the third channel region, and a fourth transistor including a fourth channel region formed over the second charge storage structure;
a first access line in the second trench and adjacent the second side of the first memory cell;
a second access line in the second trench and adjacent the first side of the second memory cell;
a first conductive shield structure adjacent the first side of the first memory cell; and
a second conductive shield structure adjacent the second side of the second memory cell, wherein:
each of the first and second access lines and the conductive shield structure has a height in a direction perpendicular to a direction from the first memory cell to the second memory cell; and
the height of the conductive shield structure is greater than the height of each of the first and second access line.