Instruction fusion
Techniques are disclosed that relate to executing pairs of instructions. A processor may include fusion detector circuitry configured to detect a pair of fetched instructions and fuse the pair of fetched instructions into a fused instruction operation, and execution circuitry coupled to the fusion detector circuitry and configured to execute the fused instruction operation. In some embodiments the pair of instructions is executable to generate a remainder of a division operation. In some embodiments the pair of instructions is executable to compare two operands and perform a write operation based on the comparison. In some embodiments the pair of instructions is executable to perform an operation and apply a mask bit sequence to the result. The fusion detector circuitry may also be configured to obtain first and second portions of a constant value from first and second instructions and store the first and second portions in a destination register.
1. A processor, comprising:
fusion detector circuitry configured to:
receive fetched instructions;
detect a first pair of the fetched instructions, wherein the first pair includes:
a first instruction that is executable to:
perform a divide operation using a dividend from a first source register and a divisor from a second source register; and
write a quotient of the divide operation to a first destination register; and
a second instruction that is executable to:
read the quotient, the dividend and the divisor from the first destination register, the first source register and the second source register;
calculate a remainder of the divide operation; and
write the remainder to the first destination register, overwriting the quotient; and
fuse the first pair of the fetched instructions into a first fused instruction operation that is executable to use the dividend and the divisor to calculate the remainder and write the remainder instead of the quotient to the first destination register; and
execution circuitry coupled to the fusion detector circuitry and configured to execute the first fused instruction operation.
2. The processor of claim 1 , wherein the execution circuitry comprises:
a divider circuit configured to generate a set of residual values related to the remainder; and
a conversion circuit configured to convert the set of residual values into the remainder.
3. The processor of claim 1 , wherein the execution circuitry is configured to execute the first fused instruction operation without performing a multiplication operation to calculate the remainder.
4. The processor of claim 1 , wherein the second instruction is a multiply-subtract instruction that is executable to perform a multiplication of a pair of operands and to subtract a result of the multiplication from another operand, and wherein the first instruction is coded to supply the divisor and the quotient as the pair of operands to be multiplied and to supply the dividend as the other operand.
5. The processor of claim 1 , wherein
the fusion detector circuitry is further configured to:
detect a second pair of the fetched instructions, wherein the second pair is executable to write, to a second destination register, a specified portion of an arithmetic/logic operation result, and wherein the second pair includes:
a first instruction that is executable to perform an arithmetic/logic operation to produce the arithmetic/logic operation result and write the arithmetic/logic operation result to the second destination register; and
a second instruction that is executable to perform a logical AND operation of the arithmetic/logic operation result with a specified mask bit sequence and write a result of the logical AND operation to the second destination register; and
fuse the second pair of the fetched instructions into a second fused instruction operation that is executable to perform the arithmetic/logic operation and write to the second destination register the specified portion, corresponding to the specified mask bit sequence, of the arithmetic/logic operation result; and
the execution circuitry is further configured to execute the second fused instruction operation.
6. The processor of claim 5 , wherein the execution circuitry is further configured to generate the specified mask bit sequence.
7. The processor of claim 1 , wherein
the fusion detector circuitry is further configured to:
detect a second pair of the fetched instructions, wherein the second pair includes:
a first instruction that is executable to:
perform a comparison of a first operand to a second operand; and
write to one or more bits of a status register based on a result of the comparison; and
a second instruction that is executable to write a value to a second destination register based on the first operand, the second operand, and bit values of the one or more bits of the status register; and
fuse the second pair of the fetched instructions into a second fused instruction operation that is executable to perform the comparison of the first operand to the second operand and write to the second destination register based on the result of the comparison; and
the execution circuitry is further configured to execute the second fused instruction operation.
8. The processor of claim 7 , wherein the second instruction of the second pair is executable to store either the first operand or the second operand in the second destination register, based on the result of the comparison of the first operand and the second operand.
9. The processor of claim 7 , wherein the second instruction of the second pair is executable to store either a value of “0” or a value of “1” in the second destination register, based on the result of the comparison of the first operand and the second operand.
10. The processor of claim 1 , wherein the fusion detector circuitry is further configured to:
detect a second pair of the fetched instructions, wherein the second pair is executable to store into a second destination register a constant value having a bit length larger than a width of an immediate value field of a first instruction or a second instruction of the second pair;
perform a register storage operation executable to:
obtain a first portion of the constant value from the first instruction of the second pair and a second portion of the constant value from the second instruction of the second pair; and
store the first and second portions of the constant value in corresponding first and second portions of the second destination register; and
prevent instruction operations corresponding to the first instruction of the second pair and the second instruction of the second pair from being dispatched to an execution pipeline of the processor.
11. The processor of claim 10 , wherein:
the first instruction of the second pair is one of:
a move/zero instruction that is executable to write the first portion of the constant value to the first portion of the second destination register and write zeros to the second portion of the second destination register;
a move/negate instruction that is executable to write the first portion of the constant value to the first portion of the second destination register and write ones to the second portion of the second destination register;
a logical OR instruction that is executable to perform a bitwise OR operation of the first portion of the constant value with a source register filled with zeros and write a result of the bitwise OR operation to the first portion of the second destination register; or
a logical XOR instruction that is executable to perform a bitwise exclusive OR operation of the first portion of the constant value with a source register filled with zeros and write a result of the bitwise exclusive OR operation to the first portion of the second destination register; and
the second instruction of the second pair is a move/keep instruction that is executable to write the second portion of the constant value to the second portion of the second destination register without changing bit values in the first portion of the second destination register.
12. The processor of claim 10 , wherein:
the first instruction of the second pair is executable to calculate a first address of a target page in memory and write the first address to the second destination register; and
the second instruction of the second pair is executable to add an offset value to the first address to form a second address and write the second address to the second destination register.
13. A method, comprising:
detecting, by a processor, a first instruction of a first pair of instructions, wherein the first instruction of the first pair is executable by the processor to:
perform a divide operation using a dividend from a first source register and a divisor from a second source register, and
write a quotient of the divide operation to a first destination register;
detecting, by the processor, a second instruction of the first pair of instructions, wherein the second instruction of the first pair is executable by the processor to:
read the quotient, dividend and divisor from the first destination register, first source register and second source register, respectively;
calculate a remainder of the divide operation; and
write the remainder to the first destination register, overwriting the quotient;
fusing, by the processor, the first pair of instructions into a first fused instruction operation that is executable by the processor to:
use the dividend and the divisor to calculate the remainder; and
write the remainder instead of the quotient to the first destination register; and
executing, by the processor, the first fused instruction operation.
14. The method of claim 13 , further comprising:
detecting, by the processor, a first instruction of a second pair of instructions, wherein the first instruction of the second pair is executable by the processor to:
perform an arithmetic/logic operation to produce an arithmetic/logic operation result; and
write the arithmetic/logic operation result to a second destination register;
detecting, by the processor, a second instruction of the second pair of instructions, wherein the second instruction of the second pair is executable by the processor to:
perform a logical AND operation of the arithmetic/logic operation result with a specified mask bit sequence; and
write a result of the logical AND operation to the second destination register;
fusing, by the processor, the second pair of instructions into a second fused instruction operation that is executable to perform the arithmetic/logic operation and write to the second destination register a portion, corresponding to the specified mask bit sequence, of the arithmetic/logic operation result; and
executing, by the processor, the second fused instruction operation.
15. The method of claim 13 , further comprising:
detecting, by the processor, a first instruction of a second pair of instructions, wherein the first instruction of the second pair is executable by the processor to perform a comparison of a first operand to a second operand and write to one or more bits of a status register based on a result of the comparison;
detecting, by the processor, a second instruction of the second pair of instructions, wherein the second instruction of the second pair is executable by the processor to write a value to a second destination register based on the first operand, the second operand, and bit values of the one or more bits of the status register;
fusing, by the processor, the second pair of instructions into a second fused instruction operation that is executable by the processor to perform the comparison of the first operand to the second operand and write to the second destination register based on the result of the comparison; and
executing, by the processor, the second fused instruction operation.
16. The method of claim 13 , further comprising:
detecting, by the processor, a second pair of instructions executable to store into a second destination register a constant value having a bit length larger than a width of an immediate value field of a first instruction or a second instruction of the second pair of instructions;
obtaining a first portion of the constant value from the first instruction of the second pair of instructions;
obtaining a second portion of the constant value from the second instruction of the second pair of instructions;
storing the first and second portions of the constant value in corresponding first and second portions of the second destination register; and
preventing instruction operations corresponding to the first instruction and second instruction of the second pair of instructions from being dispatched to an execution pipeline of the processor.