Bias voltage schemes during pre-programming and programming phases

1. A method comprising:

causing, by a processing device, a first bias voltage with respect to a first dummy wordline of a set of dummy wordlines of a memory array to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, wherein the first dummy wordline is adjacent to a select gate of the memory array;

maintaining, by the processing device, the first bias voltage at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase, wherein the first bias voltage is ramped from the power supply voltage to the first dummy wordline seed voltage; and

causing, by a processing device during a programming phase, the first bias voltage to be ramped from the first dummy wordline seed voltage to a program inhibit bias voltage.

2. The method of claim 1 , wherein the causing the first bias voltage to be ramped to the power supply voltage during the seed first sub-phase further comprises simultaneously ramping a select gate bias voltage with respect to the select gate and the first bias voltage from 0 V to the power supply voltage.

3. The method of claim 1 , wherein causing the first bias voltage to be ramped to the power supply voltage during the seed first sub-phase further comprises causing the first bias voltage to be ramped to the power supply voltage before ramping a select gate bias voltage with respect to the select gate from 0 V to the power supply voltage.

4. The method of claim 1 , wherein the set of dummy wordlines further comprises a second dummy wordline adjacent to the first dummy wordline, and a third dummy wordline adjacent to the second dummy wordline.

5. The method of claim 4 , further comprising:

causing, by the processing device, a second bias voltage with respect to the second dummy wordline and a third bias voltage with respect to the third dummy wordline to be ramped from the power supply voltage to a second dummy wordline seed voltage and a third dummy wordline seed voltage, respectively.

6. The method of claim 5 , further comprising:

causing, by the processing device prior to the bitline setting sub-phase, the second bias voltage and the third bias voltage to each be ramped down to 0 V from the second dummy wordline seed voltage and the third dummy wordline seed voltage, respectively.

7. The method of claim 1 , wherein the first bias voltage is ramped from the first dummy wordline seed voltage to the first program inhibit bias voltage in accordance with a first set of step-up voltage parameters, and wherein the first set of step-up voltage parameters comprises a first step ratio defined based on a change in programming pulse voltage.

8. A memory device comprising:

a memory array comprising a select gate, and a set of memory cells corresponding to a set of dummy wordlines, the set of dummy wordlines comprising a first dummy wordline adjacent to the select gate; and

control logic, operatively coupled with the memory array, to perform memory programming operations comprising at least one of:

causing a first bias voltage with respect to the first dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase;

maintaining the first bias voltage at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase, wherein the first bias voltage is ramped from the power supply voltage to the first dummy wordline seed voltage; and

causing, during a programming phase, the first bias voltage to be ramped from the first dummy wordline seed voltage to a program inhibit bias voltage.

9. The memory device of claim 8 , wherein causing the first bias voltage to be ramped to the power supply voltage during the seed first sub-phase further comprises simultaneously ramping a select gate bias voltage with respect to the select gate and the first bias voltage from 0 V to the power supply voltage.

10. The memory device of claim 8 , wherein causing the first bias voltage to be ramped to the power supply voltage during the seed first sub-phase further comprises causing the first bias voltage to be ramped to the power supply voltage before ramping a select gate bias voltage with respect to the select gate from 0 V to the power supply voltage.

11. The memory device of claim 8 , wherein the set of dummy wordlines further comprises a second dummy wordline adjacent to the first dummy wordline, and a third dummy wordline adjacent to the second dummy wordline.

12. The memory device of claim 11 , wherein the memory programming operations further comprise causing a second bias voltage with respect to the second dummy wordline and a third bias voltage with respect to the third dummy wordline be ramped from the power supply voltage to a second dummy wordline seed voltage and a third dummy wordline seed voltage, respectively.

13. The memory device of claim 12 , wherein the memory programming operations further comprise causing, prior to the bitline setting sub-phase, the second bias voltage and the third bias voltage to each be ramped down to 0 V from the second dummy wordline seed voltage and the third dummy wordline seed voltage, respectively.

14. A method comprising:

causing, by a processing device, a bias voltage with respect to each dummy wordline of a set of dummy wordlines to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, wherein the set of dummy wordlines comprises a first dummy wordline adjacent to a select gate;

causing, by the processing device, the bias voltage with respect to the first dummy wordline to be ramped from the power supply voltage to a first dummy wordline seed voltage;

maintaining, by the processing device, the bias voltage with respect to the first dummy wordline at the first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase; and

causing, by the processing device, the bias voltage with respect to the first dummy wordline to be ramped from the first dummy wordline seed voltage to a first program inhibit bias voltage in accordance with a first set of step-up voltage parameters, wherein the first set of step-up voltage parameters comprises a first step ratio defined based on a change in programming pulse voltage.

15. The method of claim 14 , wherein the first set of step-up voltage parameters further comprises an initial program inhibit bias voltage value and a maximum program inhibit bias voltage value, and wherein the first step ratio is defined based on a change in programming pulse voltage.

16. The method of claim 14 , wherein the set of dummy wordlines further a second dummy wordline adjacent to the first dummy wordline, and a third dummy wordline adjacent to the second dummy wordline.

17. The method of claim 16 , further comprising:

causing, by the processing device, the bias voltage with respect to the second dummy wordline and the bias voltage with respect to the third dummy wordline to be ramped from 0 V to a second program inhibit bias voltage and third program inhibit bias voltage, respectively;

wherein the first program inhibit bias voltage is less than the second program inhibit bias voltage, and the second program inhibit bias voltage is less than the third program inhibit bias voltage.

18. The method of claim 16 , further comprising causing, by the processing device prior to the bitline setting sub-phase, the bias voltage with respect to the second dummy wordline and the bias voltage with respect to the third dummy wordline to each be ramped down to 0 V from a second dummy wordline seed voltage and a third dummy wordline seed voltage, respectively.

19. The method of claim 14 , further comprising causing, by the processing device, a select gate bias voltage with respect to the select gate to be ramped from 0 V to the power supply voltage either simultaneously with, or after, causing the bias voltage of each dummy wordline of the set of dummy wordlines to be ramped from 0 V to the power supply voltage.