Nonvolatile memory device including combined sensing node and cache read method thereof
A cache read method of a nonvolatile memory device including a plurality of page buffer units and cache latches, each page buffer units having a sensing latch and a sensing node line is provided. The method comprises performing a first on-chip valley search (OVS) read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units; storing first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read; dumping the first data to sensing node lines of at least one page buffer unit, excluding the first page buffer unit, from among the plurality of page buffer units; and performing a second OVS read on the selected memory cell using the first sensing latch.
1. A cache read method of a nonvolatile memory device including a memory cell array, a plurality of page buffer units, and cache latches, each of the plurality of page buffer units having a sensing latch and a sensing node line, the method comprising:
performing a first on-chip valley search (OVS) read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units;
storing, during a program suspend period, first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read;
transferring the first data to sensing node lines of at least one page buffer unit, from a remainder of the plurality of page buffer units; and
performing a second OVS read on the selected memory cell using the first sensing latch,
wherein, during the program suspend period, the plurality of page buffer units are occupied by write data of a suspended program operation.
2. The method of claim 1 , further comprising:
connecting the first sensing node line of the first page buffer unit to a sensing node line of each of the plurality of page buffers units according to a pass control signal; and
transmitting a result of the second OVS read to a page buffer decoder in response to a common pass control signal,
wherein the sensing node lines of the plurality of page buffer units are connected to each other by pass transistors, the pass transistors configured to be switched on or off according to the pass control signal.
3. The method of claim 2 , wherein the transferring the first data includes:
turning on one of the pass transistors of at least one of the plurality of page buffer units to electrically connect the sensing node lines of the at least one page buffer unit and another of the plurality of page buffer units;
precharging the sensing node lines of the at least one page buffer unit; and
setting, based on the first data, at least one of a read voltage or development time applied to the precharged sensing node lines.
4. The method of claim 2 , wherein transferring the result of the second OVS read from the first sensing latch to the page buffer decoder includes deactivating the pass control signal and activating the common pass control signal.
5. The method of claim 1 , further comprising:
returning the first data stored in the sensing node lines of the at least one page buffer unit to the first sensing latch after the second OVS read is completed.
6. The method of claim 5 , further comprising:
sensing second data stored in the selected memory cell based on the result of the second OVS read.
7. The method of claim 1 , wherein the cache read method of the nonvolatile memory device is performed in a program suspend period of the nonvolatile memory device.
8. A nonvolatile memory device comprising:
a cell array comprising a plurality of memory cells serially coupled to bit lines;
a page buffer circuit including a plurality of page buffer units configured to program or sense at least one of the plurality of memory cells through the bit lines and electrically connect or block adjacent sensing node lines in response to a pass control signal; and
a control circuit configured to
suspend a program operation, and
while the program operation is suspended, move first data corresponding to a first state sensed through a first sensing node line in a first sensing latch of a first page buffer unit to a second sensing node line of a second page buffer unit during a cache read operation, and to control the page buffer circuit such that the first sensing latch performs an on-chip valley search (OVS) for reading a second state of the first sensing node line,
wherein, while the program operation is suspended, the plurality of page buffer units are occupied by write data of the program operation.
9. The device of claim 8 , wherein each of the plurality of page buffer units includes at least one pass transistor configured to, in response to the pass control signal, electrically connect or block an adjacent sensing node line of an adjacent page buffer unit.
10. The device of claim 9 , wherein the first data is moved to sensing node lines of at least two page buffer units including the second page buffer unit.
11. The device of claim 10 , wherein the at least two page buffer units correspond to an unused page buffer unit during the OVS for reading the second state.
12. The device of claim 9 , wherein a level of the pass control signal is greater than or equal to a sum of an internal power supply voltage and a threshold voltage of the corresponding at least one pass transistor.
13. The device of claim 8 , wherein the first data corresponds to fine sensed data under a bias condition determined based on a result of a prior OVS for reading the first state.
14. The device of claim 8 , wherein the control circuit is configured to control the page buffer circuit to return the first data from the second sensing node line to the first sensing latch when the first sensing latch completes the on-chip valley search for reading the second state.
15. The device of claim 8 , wherein the page buffer circuit includes:
a plurality of cache units configured to transfer sensing data, sensed during the OVS, of each of the plurality of page buffer units to an output terminal; and
a page buffer decoder configured to provide data sensed by the first sensing latch from the OVS to a wired OR terminal.
16. The device of claim 15 , wherein the first page buffer unit includes:
a first pass transistor configured to connect the first sensing node line to the second sensing node line in response to the pass control signal; and
a second pass transistor configured to connect the first sensing node line to the wired or terminal in response to a common pass control signal.
17. A cache read method of a nonvolatile memory device, comprising:
initiating a program suspend period by suspending a program operation;
storing first data in a sensing latch of a first page buffer unit of a plurality of buffer units, the first data sensed from a selected memory cell;
transferring, during the program suspend period, the first data from the sensing latch of the first page buffer unit to a sensing node line of a second page buffer unit of the plurality of buffer units; and
performing an on-chip valley search (OVS) on the selected memory cell using the sensing latch,
wherein, during the program suspend period, the plurality of page buffer units are occupied by write data of a suspended program operation.
18. The method of claim 17 , wherein the first data is data sensed under a bias condition set according to a result of a prior OVS for the selected memory cell.
19. The method of claim 17 , wherein the second page buffer unit includes at least two page buffer units, and the sensing node line corresponds to a combined sensing node electrically connecting the sensing node lines of the at least two page buffer units.
20. The method of claim 17 , further comprising:
transferring the first data dumped to the sensing node line to the sensing node line of the second page buffer unit after the OVS is completed.