Molded silicon interconnects in bridges for integrated-circuit packages
Disclosed embodiments include silicon interconnect bridges that are in a molded frame, where the molded frame includes passive devices and the silicon interconnect bridge includes through-silicon vias that couple to a redistribution layer on both the silicon interconnect bridge and the molded frame.
1. An integrated-circuit (IC) package structure, comprising:
a silicon interconnect bridge in a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the silicon interconnect bridge shares the die side;
a passive device in the molding-mass frame, wherein the silicon interconnect bridge and the passive device occupy at least some of the same vertical space encompassed by the molding-mass frame; and
a redistribution layer on the die side, wherein the redistribution layer is coupled to the passive device and to a through-silicon via in the silicon interconnect bridge, wherein the through-silicon via is communicatively coupled to the package side, wherein the redistribution layer is coupled at the die side to a first IC die by a first electrical bump and to a second IC die by a second electrical bump, and wherein communication between the first IC die and the second IC die is by the through-silicon via in the silicon interconnect bridge.
2. The IC package structure of claim 1 , further comprising:
a package substrate comprising a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material,
wherein the bridge side of the package substrate is coupled to the package side through an electrical bump.
3. The IC package structure of claim 1 , wherein communication between the first IC die and the second IC die is further by a trace in the redistribution layer.
4. The IC package structure of claim 1 , wherein the passive device is both coupled to the die side and to the package side.
5. The IC package structure of claim 1 , further comprising:
a package substrate comprising a bridge side and a land side, wherein the bridge side of the package substrate is coupled to the package side; and
a board coupled to the package substrate at the land side.
6. An integrated-circuit (IC) package structure, comprising:
a first silicon interconnect bridge in a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the first silicon interconnect bridge shares the die side;
a second silicon interconnect bridge in the molding-mass frame, wherein some molding-mass material of the molding-mass frame, spaces apart the first silicon interconnect bridge from the second silicon interconnect bridge, and wherein the second silicon interconnect bridge also shares the die side;
an interstitial passive device in the molding-mass material between the first silicon interconnect bridge and the second silicon interconnect bridge, wherein the first and second silicon interconnect bridges and the interstitial passive device occupy at least some of the same vertical space encompassed by the molding-mass frame, and wherein the interstitial passive device is a first capacitor that is both coupled to the die side and to the package side;
a redistribution layer on the die side, wherein the redistribution layer is coupled to the interstitial passive device and to a first through-silicon via in the first silicon interconnect bridge, and wherein the first through-silicon via communicates to the package side, wherein the redistribution layer is coupled to the interstitial passive device and to a second through-silicon via in the second silicon interconnect bridge, and wherein the second through-silicon via is communicatively coupled to the package side;
a second capacitor in the molding-mass material and adjacent the first silicon interconnect bridge and opposite the interstitial passive device; and
a third capacitor in the molding-mass material and adjacent the second silicon interconnect bridge and opposite the interstitial passive device.
7. The IC package structure of claim 6 , further comprising:
a second capacitor and a third capacitor in the molding-mass material and adjacent the first silicon interconnect bridge and opposite the interstitial passive device, wherein the second capacitor and the third capacitor are contacted at respective power terminals, to form a first power rail.
8. The IC package structure of claim 7 , further comprising:
a fourth capacitor, wherein the fourth capacitor contacts the third capacitor to form a Vss rail, and wherein the third capacitor is stacked on the second capacitor and the fourth capacitor.
9. The IC package structure of claim 6 , further comprising:
a package substrate comprising a bridge side and a land side, wherein the bridge side of the package substrate is coupled to the package side; and
a board coupled to the package substrate at the land side.
10. A computing system, comprising:
a silicon interconnect bridge in a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the silicon interconnect bridge shares the die side;
a first integrated-circuit (IC) die on the die side, wherein the first IC die is a logic processor;
a second IC die on the die side and adjacent the first IC die, wherein the second IC die is a graphics processor;
a passive device in the molding-mass frame, wherein the silicon interconnect bridge and the passive device occupy at least some of the same vertical space encompassed by the molding-mass frame;
a redistribution layer on the die side, wherein the redistribution layer is coupled to the passive device and to a through-silicon via in the silicon interconnect bridge, and wherein the through-silicon via is communicatively coupled to the package side; and
a package substrate comprising a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material,
wherein the bridge side of the package substrate is coupled to the package side through an electrical bump,
wherein the redistribution layer is coupled at the die side to the first IC die by a first electrical bump and to the second IC die by a second electrical bump, and wherein communication between the first IC die and the second IC die is by a trace in the redistribution layer, and
wherein the silicon interconnect bridge is part of a chipset.
11. The computing system of claim 10 , further comprising:
a third IC die on the redistribution layer, wherein the third IC die is a memory die; and
a board coupled to the package substrate at the land side by an electrical-bump array.
12. The computing system of claim 11 , wherein the board comprises an external shell that is a dielectric material, and wherein the external shell is at least part of an exterior of an apparatus selected from a mobile computing system and a drone.
13. An integrated-circuit (IC) package structure, comprising:
a silicon interconnect bridge in a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the silicon interconnect bridge shares the die side;
a first capacitor in the molding-mass frame, wherein the silicon interconnect bridge and the first capacitor occupy at least some of the same vertical space encompassed by the molding-mass frame;
a second capacitor, wherein the first capacitor and the second capacitor are contacted at respective power terminals, to form a power rail; and
a redistribution layer on the die side, wherein the redistribution layer is coupled to the first capacitor and to a through-silicon via in the silicon interconnect bridge, and wherein the through-silicon via is communicatively coupled to the package side.
14. The IC package structure of claim 13 , further comprising:
a package substrate comprising a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material,
wherein the bridge side of the package substrate is coupled to the package side, and
wherein the Vcc plane is coupled to the power rail.
15. The IC package structure of claim 13 , further comprising:
a third capacitor, wherein the third capacitor contacts the second capacitor to form a Vss rail, and wherein the second capacitor is stacked on the first capacitor and the third capacitor.
16. The IC package structure of claim 15 , further comprising:
a package substrate comprising a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material,
wherein the bridge side of the package substrate is coupled to the package side through an electrical bump,
wherein the Vcc plane is coupled to the power rail, and
wherein the Vss plane is coupled to the Vss rail.
17. The IC package structure of claim 13 , further comprising:
a package substrate comprising a bridge side and a land side, wherein the bridge side of the package substrate is coupled to the package side; and
a board coupled to the package substrate at the land side.