IP Library › Granted Patent US 12,218,619
Granted Patent B2
US 12,218,619 · App. 17/989,227 · Granted Feb 4, 2025

System and method for detecting resolver signal for motor control

Inventors: Do Hyeon Ham (Goyang-si, KR); Ho Jun Shin (Incheon, KR); Hun Kong (Suwon-si, KR); Jang Ho Won (Hwaseong-si, KR)
Assignees: HYUNDAI MOTOR COMPANY; KIA CORPORATION
H02P6/188H02P21/18
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Quick Facts
Patent No.
US 12,218,619
App. No.
17/989,227
Granted
Feb 4, 2025
Kind
B2
Abstract

The present disclosure provides a system and method for detecting a resolver signal of a motor allowing accurate detection of a peak magnitude, a peak time, a peak point, etc. of a resolver output signal. A bandpass filter and a moving average processor are configured to remove noise introduced into the resolver output signal and maintain a magnitude of the resolver output signal at original magnitude without change. A phase compensation process performed by a lead phase compensator can compensate a phase delay time for the resolver output signal.

Claims (84)

1. A system for detecting a resolver signal for controlling a motor, the system comprising:

a resolver configured to generate a resolver output signal of a sine wave or a cosine wave when the motor is driven, and output the resolver output signal to a controller; and

the controller including a first bandpass filter for primarily removing noise introduced into the resolver output signal, a moving average processor for performing a continuous moving average calculation process for a resolver output signal passing through the first bandpass filter, and a lead phase compensator for compensating a phase of a resolver output signal passing through the moving average processor,

wherein the moving average processor is configured to determine the number of pieces of data for moving average for an output signal of the resolver passing through the first bandpass filter by dividing a sampling frequency of a predetermined specific period by a frequency of an output signal of the resolver.

2. The system of claim 1 , wherein, when the resolver output signal of a predetermined period passing through the first bandpass filter is sequentially input as continuous data to a preset number (n) of buffers, the moving average processor is configured to repeatedly calculate an average for each piece of sequentially input data.

3. The system of claim 1 , wherein the lead phase compensator is configured to compensate the phase of the resolver output signal after passing through the moving average processor to a phase level of a resolver output signal before passing through the moving average processor, which is an original signal.

4. The system of claim 3 , wherein the lead phase compensator is configured to determine a phase to be compensated by

G

leadComp

(

s

)

=

k

⁢

1

+

s

/

ω

o

1

+

s

/

ω

p

:

where G leadComp (s) denotes a phase to be compensated, k denotes a gain value, wo denotes the same value as a frequency value of the original signal which is the resolver output signal before passing through the moving average processor, and Op denotes a value set larger than the frequency value of the original signal.

5. The system of claim 1 , wherein the controller further includes:

a differentiator configured to differentiate and output a resolver output signal having a phase compensated by passing through the lead phase compensator;

a second bandpass filter configured to filter the differentiated resolver output signal output from the differentiator to extract a signal in a preset specific band;

a reference point detector configured to detect a point in time when the differentiated resolver output signal passing through the second bandpass filter satisfies a reference voltage;

a peak time detector configured to detect a peak time of the resolver output signal based on a point in time detected by the reference point detector;

an edge time detector configured to detect an edge time of a square wave signal;

a subtractor configured to subtract the edge time of the square wave signal detected by the edge time detector from the peak time of the resolver output signal detected by the peak time detector; and

a delay time calculator configured to calculate a phase delay time based on a peak time of the resolver output signal subtracted by the subtractor.

6. The system of claim 5 , wherein the controller further includes a limiter configured to remove a result of subtraction to prevent malfunction when the peak time of the resolver output signal subtracted by the edge time of the square wave signal by the subtractor is outside of a reference range.

7. A method for detecting a resolver signal for controlling a motor, the method comprising:

generating and outputting a resolver output signal of a sine wave or a cosine wave when the motor is driven;

primarily removing, by a first bandpass filter, noise introduced into a resolver output signal;

performing, by a moving average processor, a continuous moving average calculation process for a resolver output signal passing through the first bandpass filter;

performing, by a lead phase compensator, a process of compensating a phase of a resolver output signal passing through the moving average processor; and

determining, by the moving average processor, the number of pieces of data for moving average for an output signal of the resolver passing through the first bandpass filter by dividing a sampling frequency of a predetermined specific period by a frequency of an output signal of the resolver.

8. The method of claim 7 , wherein, when the resolver output signal of a predetermined period passing through the first bandpass filter is sequentially input as continuous data to a preset number (n) of buffers, the moving average calculation process is performed by repeatedly calculating an average for each piece of sequentially input data.

9. The method of claim 8 , wherein the moving average calculation process is performed by repeating:

a process of calculating an average for a resolver output signal of a predetermined period passing through the first bandpass filter, which is data sequentially input to the preset number (n) of buffers;

a process of excluding data input to a last buffer among the preset number (n) of buffers;

a process of moving data input to the n preset buffers to adjacent buffers;

a process of inputting new data to a first buffer among the preset number (n) of buffers; and

a process of calculating an average for data input to the preset number (n) of buffers including newly input data.

10. The method of claim 7 , wherein the process of compensating the phase is a process of compensating the phase of the resolver output signal after passing through the moving average processor to a phase level of a resolver output signal before passing through the moving average processor, which is an original signal.

11. The method of claim 10 , wherein, in the process of compensating the phase, a phase to be compensated is determined by

G

leadComp

(

s

)

=

k

⁢

1

+

s

/

ω

o

1

+

s

/

ω

p

:

where G leadComp (s) denotes a phase to be compensated, k denotes a gain value, wo denotes the same value as a frequency value of the original signal which is the resolver output signal before passing through the moving average processor, and Op denotes a value set larger than the frequency value of the original signal.

12. The method of claim 7 , further comprising:

differentiating a resolver output signal having a phase compensated by passing through the lead phase compensator;

filtering the differentiated resolver output signal to extract a signal in a preset specific band;

detecting a point in time when the differentiated resolver output signal satisfies a reference voltage;

detecting a peak time of the resolver output signal based on a detected point in time;

detecting an edge time of a square wave signal;

subtracting the detected edge time of the square wave signal from the detected peak time of the resolver output signal; and

calculating a phase delay time based on a subtracted peak time of the resolver output signal.

13. The method of claim 12 , further comprising removing a result of subtraction to prevent malfunction when the peak time of the resolver output signal subtracted by the edge time of the square wave signal is outside of a reference range.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2022
From: HAM, DO HYEON; SHIN, HO JUN; KONG, HUN; WON, JANG HO
To: HYUNDAI MOTOR COMPANY; KIA CORPORATION
Reel/Frame 061967/0678 →
Priority Claims (1)
KR 10-2022-0010341 · Jan 25, 2022 · national
Continuity (1)
Related Publication 20230238903A1 · Jul 27, 2023
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