IP Library › Granted Patent US 12,219,075
Granted Patent B2
US 12,219,075 · App. 18/115,796 · Granted Feb 4, 2025

Detection device

Inventor: Masataka Ikeda (Tokyo, JP)
Assignee: JAPAN DISPLAY INC.
H04L9/3278
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Quick Facts
Patent No.
US 12,219,075
App. No.
18/115,796
Granted
Feb 4, 2025
Kind
B2
Abstract

A detection device includes a pixel including a photodiode connected to a gate electrode of a first transistor, and a control circuit configured to control an operation of the pixel in a reset period (including a first and a second periods) for resetting the gate electrode, an exposure period for exposing the photo diode, and a read-out period (a fourth period) to read out a voltage associated with the exposure of the photodiode. The control circuit is configured to read out a first voltage during the first period, read out a second voltage during the second period after stopping a supply of a reset voltage to the gate electrode, read out a third voltage in the fourth period after the exposure period, output a difference value between the first and the second voltages as PUF-ID data and a difference value between the third and the second voltages as detection data.

Claims (40)

1. A detection device comprising:

at least one pixel including a first electrode of a photo diode connected to a gate electrode of a first transistor connected between a power supply line and a read-out signal line; and

a control circuit configured to control an operation of the at least one pixel in each of a reset period for resetting the gate electrode of the first transistor, an exposure period for exposing the photo diode, and a read-out period to read out a voltage associated with the exposure of the photo diode,

wherein, the control circuit is configured to:

read out a first voltage from the read-out signal line during a first period of supplying a reset voltage to the gate electrode of the first transistor;

read out a second voltage from the read-out signal line during a second period after stopping a supply of the reset voltage to the gate electrode of the first transistor;

read out a third voltage from the read-out signal line in a fourth period being the read-out period after a third period being the exposure period;

output a difference value between the first voltage and the second voltage as PUF-ID data; and

output a difference value between the third voltage and the second voltage as detection data, in the reset period.

2. The detection device according to claim 1 , further comprising a plurality of pixels including the at least one pixel,

wherein, each of the plurality of pixels is configured to execute the reading of the first voltage, the second voltage, and the third voltage.

3. The detection device according to claim 1 , further comprising a second transistor connected between a reset voltage line and the gate electrode of the first transistor,

wherein, the control circuit is configured to control:

turning on the second transistor; and

supplying the reset voltage from the reset voltage line to the gate electrode of the first transistor.

4. The detection device according to claim 3 , further comprising a third transistor connected between an electrode not connected to a power supply line among a pair of electrodes, and a read-out signal line,

wherein, the control circuit is configured to control:

turning on the third transistor; and

reading the first voltage, the second voltage, and the third voltage.

5. The detection device according to claim 4 , further comprising a fourth transistor connected between the read-out signal line and a reference potential line,

wherein, the control circuit is configured to control:

supplying a bias voltage to a gate electrode of the fourth transistor;

turning on the fourth transistor; and

passing a constant current between a pair of electrodes of the fourth transistor.

6. The detection device according to claim 5 , wherein

the first transistor, the third transistor, and the fourth transistor constitute a source follower, and

the control circuit is configured to control:

turning on the first transistor, the third transistor, and the fourth transistor; and

passing a current between the power supply line and the read-out signal line.

7. The detection device according to claim 6 , further comprising a fifth transistor connected between the gate electrode of the first transistor and the first electrode of the photo diode;

wherein, the control circuit is configured to control:

turning on the fifth transistor; and

supplying a voltage generated by the exposure of the photo diode to the gate electrode of the first transistor, in the third period.

8. The detection device according to claim 1 , wherein

a difference value between the first voltage and the second voltage is a feed through voltage.

9. The detection device according to claim 1 , wherein

the control circuit is configured to control generating the detection data after generating the PUF-ID data.

10. The detection device according to claim 1 , wherein

the second voltage is lower than the first voltage, and

the third voltage is lower than the second voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2023
From: IKEDA, MASATAKA
To: JAPAN DISPLAY INC.
Reel/Frame 062840/0193 →
Priority Claims (1)
JP 2020-151570 · Sep 9, 2020 · national
Continuity (2)
Continuation PCTJP2021030162 · Aug 18, 2021
Related Publication 20230208658A1 · Jun 29, 2023
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