Timestamp alignment across multiple computing nodes
Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.
1. An apparatus comprising:
a network interface device comprising:
a first interface to a first processor and
circuitry to receive a time stamp from the first processor by the first interface, wherein:
receipt of the time stamp from the first processor by the first interface is to cause the circuitry to provide, to the first processor, a time stamp value based on a clock signal from a clock source corresponding to the received time stamp from the first processor and
the first processor is to adjust a time stamp counter value based, at least in part, on the time stamp value based on the clock signal corresponding to the received time stamp from the first processor.
2. The apparatus of claim 1 , wherein the first processor is to adjust a time stamp counter value based, at least in part, on the time stamp value based on the clock signal corresponding to the received time stamp from the first processor based on a linear relationship.
3. The apparatus of claim 1 , wherein the network interface device comprises
a second interface to a second processor and
circuitry is to receive a time stamp from the second processor by the second interface.
4. The apparatus of claim 3 , wherein
the second processor is to adjust a time stamp counter value based, at least in part, on the time stamp value based on the clock signal corresponding to a received time stamp from the second processor.
5. The apparatus of claim 1 , wherein
the first interface is to operate consistent with Peripheral Component Interconnect express (PCIe).
6. A method comprising:
a first processor node providing first and second time stamp counter (TSC) values to a network interface device to cause the network interface device to provide a first TSC value-primary timer value pair to the first processor node and provide a second TSC value-primary timer value pair to the first processor node;
the first processor node determining a first offset of the first TSC for the first processor node relative to the primary timer based on the first and second TSC value-primary timer value pairs received from the network interface device; and
the first processor node adjusting values of the TSC for the first processor node based on the first offset.
7. The method of claim 6 , comprising:
a second processor node providing first and second TSC values to the network interface device to cause the network interface device to provide a first TSC value-primary timer value pair to the second processor node and provide a second TSC value-primary timer value pair to the second processor node;
the second processor node determining a second offset of the TSC values for the second processor node relative to the primary timer; and
the second processor node adjusting the TSC values for the second processor node based on the second offset.
8. The method of claim 6 , wherein the primary timer is based on a network source based on IEEE 1588 or a global positioning system (GPS) signal.
9. The method of claim 6 , wherein the first offset comprises a linear offset.
10. The method of claim 7 , wherein the first offset comprises a linear offset and the second offset comprises a linear offset.
11. The method of claim 6 , wherein the first processor node utilizes a first crystal oscillator to generate the first and second TSC values for the first processor node.
12. The method of claim 7 , wherein the second processor node utilizes a second crystal oscillator to generate the first and second TSC values for the second processor node.
13. An apparatus comprising:
a first processor node comprising a first processor and a first time stamp counter (TSC) source, wherein:
by a copy of a first value of the first TSC source to a network interface device, the first processor node is to initiate and cause the network interface device to transfer a primary time stamp value recorded for the first value of the first TSC source from the network interface device to the first processor node.
14. The apparatus of claim 13 , wherein:
the first processor node is to determine a first offset for the first TSC source based, at least, in part on the primary time stamp values recorded for the first and second values of the first TSC source and
the first processor comprises one or more of: a central processing unit (CPU), core, graphics processing unit (GPU), field programmable gate array (FPGA), or application specific integrated circuit (ASIC).
15. The apparatus of claim 14 , wherein the first processor node is to execute an virtualized execution environment with time stamps that are synchronized based on the first offset.
16. The apparatus of claim 13 , comprising:
a second processor node comprising a second processor and a second TSC source, wherein the second processor comprises one or more of: a central processing unit (CPU), core, graphics processing unit (GPU), field programmable gate array (FPGA), or application specific integrated circuit (ASIC) and wherein the second processor node is to determine a second offset for a second TSC source based, at least, in part on the primary time stamp values recorded for the first and second values of the second TSC source.
17. The apparatus of claim 13 , comprising a computer, a rack, or a data center and wherein the computer, the rack, or the data center comprises the first processor node.
18. The apparatus of claim 13 , wherein at least one primary time stamp value is based on a network source based on IEEE 1588 or a global positioning system (GPS) signal.
19. The apparatus of claim 13 , wherein the first processor node is to use a first crystal oscillator to generate the first value of the first TSC source.
20. The apparatus of claim 1 , wherein:
the first processor comprises one or more of: a central processing unit (CPU), core, graphics processing unit (GPU), field programmable gate array (FPGA), or application specific integrated circuit (ASIC).
21. The apparatus of claim 3 , wherein:
the second processor comprises one or more of: a central processing unit (CPU), core, graphics processing unit (GPU), field programmable gate array (FPGA), or application specific integrated circuit (ASIC).