Granted Patent B2

US 12,222,892 · App. 17/842,129 · Granted Feb 11, 2025

Inventors: Sean Gregory Gibb (Calgary, CA); Saeed Fouladi Fard (Calgary, CA)

Assignee: Eidetic Communications Inc.

G06F15/163G06F9/3877

Abstract

Claims (86)

1. A data processing system for performing a sequence of data operations, comprising:

a plurality of data processing circuits each configured to perform a respective data operation;

a target central processing unit (CPU) configured to generate a current prefix, the current prefix including a current sequentially ordered list of the plurality of data processing circuits corresponding to the sequence of data operations;

an interconnect circuit that is separate from the target CPU, the interconnect circuit in communication with the plurality of data processing circuits and the target CPU, the interconnect circuit configured to:

receive from the target CPU the current prefix;

receive from an input data source a current data payload to be processed;

generate a current data packet by prepending the current prefix to the current data payload; and

sequentially send the current data packet to the plurality of data processing circuits by:

i) determining, based on a next entry in the current sequentially ordered list included in the current prefix of the current data packet, a one of the plurality of data processing circuits associated with the next entry;

ii) removing the next entry and an associated set of parameters from the current prefix to generate an updated prefix;

iii) replacing the current prefix with the updated prefix in the current data packet;

iv) sending the current data packet to the one of the plurality of data processing circuits associated with the next entry in the current sequentially ordered list included in the current prefix, together with the associated set of parameters;

v) receiving from the one of the plurality of data processing circuits an updated data packet including the updated prefix and a processed data payload generated by the one of the plurality of data processing circuits using the current data payload and the associated set of parameters;

vi) in response to determining that a next entry in the updated prefix is associated with any of the plurality of data processing circuits, repeating steps i) to v) using the updated data packet as the current data packet with the updated prefix being the current prefix; and

vii) in response to determining that the next entry in the updated prefix is associated with a data destination, removing the next entry from the updated prefix in the updated data packet and sending the updated data packet with the next entry removed to the data destination;

wherein each of the plurality of data processing circuits is configured to:

receive the current data packet and the associated set of parameters from the interconnect circuit;

perform a data operation on the current data payload included in the current data packet to generate the processed data payload; and

send the updated data packet including the processed data payload and the updated prefix to the interconnect circuit;

wherein:

each entry in the current sequentially ordered list comprises an address of the one of the plurality of data processing circuits associated with that entry;

the plurality of data processing circuits comprise two or more data processing circuits configured to perform a same data operation;

a first address in the current sequentially ordered list is a virtual address associated with the same data operation; and

when the next entry in the current sequentially ordered list comprises the first address, the interconnect circuit being configured to send the current data packet to the one of the plurality of data processing circuits associated with the next entry in the current sequentially ordered list comprises the interconnect circuit being configured to:

determine an available one of the two or more data processing circuits configured to perform the same data operation;

replace the first address in the next entry with an actual address of the available one of the two or more data processing circuits configured to perform the same data operation; and

send the current data packet that includes the actual address to the available one of the two or more data processing circuits.

2. The data processing system of claim 1 , wherein:

the current prefix includes a corresponding set of parameters for each entry in the current sequentially ordered list;

the interconnect circuit configured to send the current data packet to the one of the plurality of data processing circuits associated with the next entry comprises the interconnect circuit configured to send the current data packet to the one of the plurality of data processing circuits associated with the next entry together with the corresponding set of parameters; and

the one of plurality of data processing circuits being configured to perform the data operation on the current data payload comprises the one of the plurality of data processing circuits being configured to perform the data operation on the current data payload utilizing the corresponding set of parameters.

3. The data processing system of claim 1 , wherein:

each of the plurality of data processing circuits is further configured to generate a postfix that includes information associated with a status of the data operation performed by that data processing circuit; and

each of the plurality of data processing circuits being configured to send the updated data packet to the interconnect circuit comprises each of the plurality of data processing circuits sending the postfix together with the processed data payload and the updated prefix as the updated data packet.

4. The data processing system of claim 3 , wherein:

the current data packet includes a current postfix;

the interconnect circuit being configured to send the current data packet to the one of the plurality of data processing circuits associated with the next entry comprises the interconnect circuit sending the current data payload, the updated prefix, and the current postfix; and

each of the plurality of data processing circuits being configured to generate the postfix comprises each of the plurality of data processing circuits adding a postfix that includes information associated with a status of the data operation performed by that data processing circuit to the current postfix received from the interconnect circuit to generate an updated postfix.

5. The data processing system of claim 4 , wherein:

the interconnect circuit being configured to receive the updated data packet from the one of the plurality of data processing circuits comprises the interconnect circuit being configured to receive the updated postfix together with the processed data payload and the updated prefix as the updated data packet; and

the interconnect circuit being configured to repeat steps i) to v) using the updated data packet as the current data packet with the updated prefix being the current prefix comprises the interconnect circuit being configured to repeat steps i) to v) using the updated postfix received from the one of the plurality of data processing circuits as the current postfix in the current data packet.

6. The data processing system of claim 1 , wherein:

at least one of the plurality of data processing circuits is further configured to revise the updated prefix received from the interconnect circuit to generate a revised prefix, the revised prefix including at least one of a revised sequentially ordered list or a revised set of parameters associated with an entry in the current sequentially ordered list; and

the at least one of the plurality of data processing circuits being configured to send the updated data packet including the processed data payload and the updated prefix to the interconnect circuit comprises including the revised prefix as the updated prefix in the updated data packet.

7. The data processing system of claim 1 , wherein a second address of the one of the plurality of data processing circuits associated with a given entry comprises a port number associated with a port of the interconnect circuit that is connected to the one of the plurality of data processing circuits associated with the given entry.

8. A method for performing a sequence of data operations in a data processing system having a target central processing unit (CPU), an interconnect circuit separate from the target CPU, and a plurality of data processing circuits, the method comprising:

generating, by the target CPU, a current prefix, the current prefix including a current sequentially ordered list of the plurality of data processing circuits corresponding to the sequence of data operations;

receiving, at the interconnect circuit, the current prefix from the target CPU;

receiving, at the interconnect circuit, from an input data source a current data payload to be processed;

generating, by the interconnect circuit, a current data packet by prepending the current prefix to the current data payload; and

sequentially sending, by the interconnect circuit, the current data packet to the plurality of data processing circuits by:

i) determining, by the interconnect circuit, based on a next entry in the current sequentially ordered list included in the current prefix of the current data packet, a one of the plurality of data processing circuits associated with the next entry;

ii) removing, by the interconnect circuit, the next entry and an associated set of parameters from the current prefix to generate an updated prefix;

iii) replacing, by the interconnect circuit, the current prefix with the updated prefix in the current data packet;

iv) sending, by the interconnect circuit, the current data packet to the one of the plurality of data processing circuits associated with the next entry in the current sequentially ordered list included in the current prefix, together with the associated set of parameters;

v) receiving, by the interconnect circuit, from the one of the plurality of data processing circuits an updated data packet including the updated prefix and a processed data payload generated by the one of the plurality of data processing circuits using the current data payload and the associated set of parameters;

vi) in response to determining that a next entry in the updated prefix is associated with any of the plurality of data processing circuits, repeating, by the interconnect circuit, steps i) to v) using the updated data packet as the current data packet with the updated prefix being the current prefix; and

vii) in response to determining that the next entry in the updated prefix is associated with a data destination, removing, by the interconnect circuit, the next entry from the updated prefix in the updated data packet and sending, by the interconnect circuit, the updated data packet with the next entry removed to the data destination;

receiving, by the one of the plurality of data processing circuits, the current data packet and the associated set of parameters from the interconnect circuit;

performing, by the one of the plurality of data processing circuits, a data operation on the current data payload included in the current data packet to generate a processed data payload; and

sending, by the one of the plurality of data processing circuits, the updated data packet including the processed data payload and the updated prefix to the interconnect circuit;

wherein:

each entry in the current sequentially ordered list comprises an address of the one of the plurality of data processing circuits associated with that entry;

the plurality of data processing circuits comprise two or more data processing circuits configured to perform a same data operation;

a first address in the current sequentially ordered list is a virtual address associated with the same data operation performed by the two or more data processing circuits; and

when the next entry in the current sequentially ordered list comprises the first address, sending the current data packet to the one of the plurality of data processing circuits associated with the next entry in the current sequentially ordered list comprises:

determining, by the interconnect circuit, an available one of the two or more data processing circuits configured to perform the same data operation;

replacing the first address in the next entry with an actual address of the available one of the two or more data processing circuits configured to perform the same data operation; and

sending the current data packet to the available one of the two or more data processing circuits.

9. The method of claim 8 , wherein:

the current prefix includes a corresponding set of parameters for each entry in the current sequentially ordered list;

sending, by the interconnect circuit, the current data packet to the one of the plurality of data processing circuits associated with the next entry comprises sending the current data packet to the one of the plurality of data processing circuits associated with the next entry together with the corresponding set of parameters; and

performing, by the one of the data processing circuits, a data operation on the current data payload comprises performing the data operation on the current data payload utilizing the corresponding set of parameters.

10. The method of claim 8 , further comprises:

generating, by the one of the plurality of data processing circuits, a postfix that includes information associated with a status of the data operation performed by the data processing circuit; and

wherein sending, by the one of the plurality of processing circuits, the updated data packet to the interconnect circuit comprises sending the postfix together with the processed data payload and the updated prefix as the updated data packet.

11. The method of claim 10 , wherein:

the current data packet includes a current postfix;

sending the current data packet to the one of the plurality of data processing circuits associated with the next entry comprises sending, by the interconnect circuit, the current data payload, the updated prefix, and the current postfix; and

generating the postfix comprises adding, by the one of the plurality of processing circuits, a postfix that includes information associated with a status of the data operation performed by the data processing circuit to the current postfix received from the interconnect circuit to generate an updated postfix.

12. The method of claim 11 , wherein:

receiving the updated data packet from the one of the plurality of data processing circuits comprises receiving, by the interconnect circuit, the updated postfix together with the processed data payload and the updated prefix as the updated data packet; and

repeating steps i) to v) using the updated data packet as the current data payload with the updated prefix being the current prefix comprises repeating, by the interconnect circuit, steps i) to v) using the updated postfix received from the one of the plurality of data processing circuits as the current postfix in the current data payload.

13. The method of claim 8 , further comprising, during at least one of the data operations, revising, by the one of the plurality of data processing circuits, the updated prefix received from the interconnect circuit to generate a revised prefix, the revised prefix including at least one of a revised sequentially ordered list or a revised set of parameters associated with an entry in the current sequentially ordered list; and

wherein sending the updated data packet including the processed data payload and the updated prefix to the interconnect circuit comprises including, by the one of the plurality of data processing circuits, the revised prefix as the updated prefix in the updated data packet.

14. The method of claim 8 , wherein a second address of the one of the plurality of data processing circuits associated with a given entry comprises a port number associated with a port of the interconnect circuit that is connected to the one of the plurality of data processing circuits associated with the given entry.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (12)