Systems and methods for coordinating processing of scheduled instructions across multiple components
The disclosed embodiments relate to implementation of a trading system or trading system architecture having multiple transaction processors that execute financial transactions as well as scheduled tasks. The multiple transaction processors perform all actions independently of each other, but can be configured to execute the financial transactions or scheduled tasks in a controlled, coordinated, and/or synchronized manner based on time signal data augmented to the financial transactions or scheduled tasks by a transaction receiver/orderer.
1. A computer implemented method comprising:
receiving, by each of a plurality of independently operating processors from one or more receivers coupled therewith, a data message comprising signal data, wherein each processor is coupled with a memory in which at least one instruction has been previously stored in association with one of a plurality of different signal data; and
determining, by each of the plurality of processors, that the signal data of the received data message corresponds with the signal data associated with one of the stored at least one instruction stored in the memory coupled therewith, and based thereon processing the corresponding one of the stored at least one instruction.
2. The computer implemented method of claim 1 , wherein the signal data comprises data indicative of a relationship between a received data message and any of the plurality of data messages previously received by any of the one or more receivers, the received data message further comprising a transaction to be processed by each processor, the method further comprising processing, by each of the plurality of processors, the transaction of the received data messages in accordance with the corresponding signal data.
3. The computer implemented method of claim 1 , wherein the at least one instruction comprises an action to be taken by the processor and the corresponding particular signal data comprises a scheduled time for the processor to take the action.
4. The computer implemented method of claim 3 , wherein the determining comprises comparing, by each of the plurality of processors, the signal data of each received data message with the scheduled time corresponding to each of the stored at least one instruction and determining, based on the comparison, if the signal data of a received data message corresponds to the scheduled time corresponding to any of the stored at least one instruction.
5. The computer implemented method of claim 1 , wherein each of the plurality of processors, subsequent to having processed the same data messages in accordance with the corresponding signal data, regardless of when those data messages were processed, has an identical state based thereon.
6. The computer implemented method of claim 3 , wherein the action of the stored at least one instruction to be processed includes at least one of: performing garbage collection; updating software for the processor; enabling the processing by the processor of subsequent transactions; or disabling the processing by the processor of subsequent transactions.
7. The computer implemented method of claim 1 , wherein the data message was generated by one of the one or more receivers, the signal data comprising a time stamp generated by the one of the one or more receivers subsequent to a determination that a predetermined amount of time has elapsed since a prior receipt by at least the one of the one or more receivers of another data message.
8. The computer implemented method of claim 1 , further comprising receiving and storing in the memory, by each of the plurality of processors, the at least one instruction before receiving at least the data messages having signal data corresponding thereto.
9. The computer implemented method of claim 1 , wherein the plurality of receivers are coupled together to coordinate the signal data of the data message.
10. The computer implemented method of claim 1 , wherein the plurality of processors includes first and second processors, and wherein the method further comprises:
processing, by the first processor, a first stored at least one instruction at a first time; and
processing, by the second processor, the first stored at least one instruction at a second time different from the first time in a same relation to the processing of the same received data message by the first processor.
11. The computer implemented method of claim 10 , wherein processing of the first stored at least one instruction by the first and second processors causes a same modification in a physical and/or functional configuration thereof.
12. A system comprising:
a plurality of independently operating processors coupled with one or more receivers, each processor being coupled with a memory in which at least one instruction has been previously stored in association with one of a plurality of different signal data and configured to:
receive a data message from one of the one or more receivers comprising signal data; and
determine that the signal data of the received data message corresponds with the signal data associated with one of the stored at least one instruction, and based thereon processing the corresponding one of the stored at least one instruction.
13. The system of claim 12 , wherein the signal data comprises data indicative of a relationship between a received data message and any of the plurality of data messages previously received by any of the one or more receivers, the received data message further comprising a transaction to be processed by each processor, the method further comprising processing, by each of the plurality of processors, the transaction of the received data messages in accordance with the corresponding signal data.
14. The system of claim 12 , wherein the at least one instruction comprises an action to be taken by the processor and the corresponding particular signal data comprises a scheduled time for the processor to take the action.
15. The system of claim 14 , wherein each of the plurality of processors is further configured to compare the signal data of each received data message with the scheduled time corresponding to each of the stored at least one instruction and determine, based on the comparison, if the signal data of a received data message corresponds to the scheduled time corresponding to any of the stored at least one instruction.
16. The system of claim 12 , wherein each of the plurality of processors, subsequent to having processed the same data messages in accordance with the corresponding signal data, regardless of when those data messages were processed, has an identical state based thereon.
17. The system of claim 14 , wherein the action of the stored at least one instruction to be processed includes at least one of: performance of garbage collection; performance of an update to software for the processor; enablement of the processing by the processor of subsequent transactions; or disablement the processing by the processor of subsequent transactions.
18. The system of claim 12 , wherein the data message was generated by one of the one or more receivers, the signal data comprising a time stamp generated by the one of the one or more receivers subsequent to a determination that a predetermined amount of time has elapsed since a prior receipt by at least the one of the one or more receivers of another data message.
19. The system of claim 12 , wherein each of the plurality of processors is further configured to receive and store the at least one instruction prior to receipt of at least the data messages having signal data corresponding thereto.
20. The system of claim 12 , wherein the plurality of receivers are coupled together to coordinate the signal data of the data message.
21. The system of claim 12 , wherein the plurality of processors includes first and second processors, and wherein the first and second processors are configured to:
process, by the first processor, a first stored at least one instruction at a first time; and
process, by the second processor, the first stored at least one instruction at a second time different from the first time in a same relation to the processing of the same received data message by the first processor.
22. The system of claim 21 , wherein processing of the first stored at least one instruction by the first and second processors causes a same modification in a physical and/or functional configuration thereof.
23. A system comprising:
means for receiving, by each of a plurality of independently operating processing means from one or more receivers coupled therewith, a data message comprising signal data, wherein each processing means is coupled with a memory in which at least one instruction has been previously stored in association with one of a plurality of different signal data; and
means for determining, by each of the plurality of processing means, that the signal data of the received data message corresponds with the signal data associated with one of the stored at least one instruction stored in the memory coupled therewith, and based thereon processing the corresponding one of the stored at least one instruction.