IP Library › Granted Patent US 12,224,005
Granted Patent B1
US 12,224,005 · App. 18/926,560 · Granted Feb 11, 2025

Lifetime mixed level non-volatile memory system

Inventor: G. R. Mohan Rao (Allen, TX)
Assignee: Vervain, LLC
G11C11/5635G06F11/1068G06F11/1072G06F12/0246G11C11/5621G11C11/5678G11C16/16G11C16/3495G11C29/52G11C29/76G06F2212/7202G11C2211/5641
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Quick Facts
Patent No.
US 12,224,005
App. No.
18/926,560
Granted
Feb 11, 2025
Kind
B1
Abstract

An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells. The controller is configured to map the logical address range to a second physical address range for the second group of physical memory cells.

Claims (24)

1. An apparatus for storing data in a nonvolatile memory, the apparatus comprising:

[a] a controller configured to erase a group of physical memory cells in the nonvolatile memory;

[b] the controller configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory;

[c] the controller configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory;

[d] the controller configured to determine if the first group of physical memory cells fails a data integrity test;

[e] if the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory, the controller writing a single bit of information per cell in the second group of physical memory cells; and

[f] the controller configured to map the logical address range to a second physical address range for the second group of physical memory cells.

2. The apparatus of claim 1 , where the controller is configured to write at least some of the information stored in the second group of physical memory cells to a third group of physical memory cells in the nonvolatile memory.

3. The apparatus of claim 2 , where the controller is configured to write multiple bits of information to each of the third group of physical memory cells.

4. The apparatus of claim 3 , where the controller is configured to map the logical address range to a third physical address for the third group of memory cells.

5. The apparatus of claim 1 , where the controller maintains a value for each physical address range.

6. The apparatus of claim 5 , where the value indicates a number of times that information is written to each physical address range.

7. The apparatus of claim 5 , where the value indicates a number of times that each physical address range is erased.

8. The apparatus of claim 5 , where the controller is configured to determine how many times a physical address range has been written to during a time interval.

9. The apparatus of claim 5 , where the controller is configured to determine how many times a physical address range has been erased during a time interval.

10. The apparatus of claim 5 , where the controller uses the value to write information that is stored as multiple bits of information per memory cell as a single bit of information per memory cell.

11. The apparatus of claim 5 , where the controller uses the value to write information that is stored as a single bit of information per memory cell as multiple bits of information per memory cell.

12. The apparatus of claim 1 , where the controller maintains a value for each logical address range.

13. The apparatus of claim 12 , where the value indicates [the] a number of times that information is written to each logical address range.

14. The apparatus of claim 12 , where the value indicates [the] a number of times that each logical address range is erased.

15. The apparatus of claim 12 , where the controller is configured to determine how many times a logical address range has been written to during a time interval.

16. The apparatus of claim 12 , where the controller is configured to determine how many times a logical address range has been erased during a time interval.

17. The apparatus of claim 12 , where the controller uses the value to write information that is stored as multiple bits of information per memory cell as a single bit of information per memory cell.

18. The apparatus of claim 12 , where the controller uses the value to write information that is stored as a single bit of information per memory cell as multiple bits of information per memory cell.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: RAO, G.R. MOHAN
To: VERVAIN, LLC
Reel/Frame 069020/0633 →
Continuity (10)
Continuation 18893328 · Sep 23, 2024
Continuation 18613466 · Mar 22, 2024
Continuation 18390193 · Dec 20, 2023
Continuation 18387546 · Nov 7, 2023
Continuation 17203385 · Mar 16, 2021
Continuation 16006299 · Jun 12, 2018
Continuation 14950553 · Nov 24, 2015
Continuation 14525411 · Oct 28, 2014
Division 13455267 · Apr 25, 2012
Provisional Application 61509257 · Jul 19, 2011
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