One time programmable (OTP) low power circuits and methods for providing bias voltages to wordlines
Embodiments herein disclose an OTP low power circuit and methods for providing bias voltages using a single regulator. The circuit includes a Bitcell, a diode drop, a charge pump, a combinational logic controller, a program current sink load, and a read current sink load. The Bitcell includes programmable word lines and read lines, and is configured to operate in either a programmable mode or a read mode. The diode drop is configured to provide a second bias voltage to drive the read lines and the single regulator is configured to provide a first bias voltage to drive the WP in the read mode. The charge pump is configured to provide a third bias voltage to drive the WP in the program mode.
1. A method for providing bias voltages to a one time programmable (OTP) low power circuit using a single regulator, the method comprising:
determining, by a combinational logic controller, whether the OTP low power circuit is in a read mode or a programmable mode;
responsive to the OTP low power circuit being in the read mode, providing, by a combinational logic controller, a first bias voltage to programmable word lines through the single regulator, and a second bias voltage to read lines, wherein the second bias voltage is generated from the single regulator and passed through current-controlled-voltage drop; and
responsive to the OTP low power circuit being in the programmable mode, providing, by the combinational logic controller, a third bias voltage to the programmable word lines from a charge pump, and the first bias voltage to the read lines from the single regulator.
2. The method of claim 1 , wherein the charge pump provides a high programming voltage as the third bias voltage to the programmable word lines.
3. The method of claim 1 , wherein a read cycle of a control signal is high when the OTP low power circuit is in the read mode.
4. The method of claim 3 , wherein a program cycle of the control signal is high when the OTP low power circuit is in the programmable mode.
5. The method of claim 1 , further comprising:
assigning, by the combinational logic controller, a valid address to the read lines for a read operation during the read mode; and
assigning, by the combinational logic controller, a valid address and a data for a program operation during the programmable mode.
6. A one time programmable (OTP) low power circuit comprising:
a single regulator configured to output a first bias voltage;
a Bitcell comprising programmable word lines and read lines, wherein the programmable word lines and the read lines are configured to operate in a programmable mode or a read mode;
a diode drop configured to receive the first bias voltage from the single regulator and to provide a second bias voltage to drive the read lines;
a charge pump configured to provide a third bias voltage;
a combinational logic controller configured to control operations of the Bitcell in the programmable mode and read mode;
a program current sink load configured to drain a load current while the programmable word lines and the read lines are driven by the third bias voltage and the first bias voltage, respectively, in the programmable mode; and
a read current sink load that is configured to drain the load current while the programmable word lines and the read lines are driven by the first bias voltage and the second bias voltage, respectively, in the read mode.
7. The OTP low power circuit of claim 6 , wherein the charge pump provides a high programming voltage as the third bias voltage to the programmable word lines.
8. The OTP low power circuit of claim 6 , wherein a read cycle of a control signal is high when the OTP low power circuit is in the read mode.
9. The OTP low power circuit of claim 6 , wherein a program cycle of the control signal is high when the OTP low power circuit is in the programmable mode.
10. A power circuit comprising:
a regulator configured to output a first bias voltage;
a diode drop configured to receive the first bias voltage and output a second bias voltage;
a charge pump configured to output a third bias voltage;
a combined logic controller; and
a one-time-programmable bit cell comprising a read line and a program line and configured to operate in a read mode or a programmable mode, wherein:
when the bit cell is in the read mode, the combined logic controller directs the second bias voltage to the read line and the first bias voltage to the program line, and
when the bit cell is in the programmable mode, the combined logic controller directs the first bias voltage to the read line, and the third bias voltage to the program line.
11. The power circuit of claim 10 , further comprising a plurality of one-time-programmable bit cells, each configured to operate in a read mode or a programmable mode.
12. The power circuit of claim 10 , wherein the power circuit includes no more than one regulator.
13. The power circuit of claim 10 , further comprising a read current sink load and a program current sink load.
14. The power circuit of claim 10 , wherein the bit cell is programmed by the third bias voltage through a gate break down process.