Semiconductor memory device
A semiconductor memory device according to an embodiment includes: a first conductive layer; a stacked body including a plurality of second conductive layers and a plurality of first insulating layers alternately stacked one by one above the first conductive layer, and including a stepped portion in which the plurality of second conductive layers is terraced; and a plate-like portion including a third conductive layer that extends in the stacked body from the stepped portion to a memory region continuously in a stacking direction and in a first direction, the plate-like portion dividing the stacked body in a second direction that crosses both the stacking direction and the first direction. The plate-like portion includes, in the stepped portion, a plurality of contact portions that is arranged intermittently in the first direction, the plurality of contact portions penetrating the stacked body and connecting with the first conductive layer.
1. A semiconductor memory device comprising:
a first conductive layer;
a stacked body including a plurality of second conductive layers and a plurality of first insulating layers alternately stacked one by one above the first conductive layer, and including a stepped portion in which the plurality of second conductive layers is terraced;
a plurality of first pillars arranged in a memory region that is away from the stepped portion in a first direction that crosses a stacking direction of the stacked body, each first pillar including a semiconductor layer that penetrates the stacked body and connects with the first conductive layer, and forming a memory cell at an intersection with at least a part of the plurality of second conductive layers; and
a plate-like portion including a third conductive layer that extends in the stacked body from the stepped portion to the memory region continuously in the stacking direction and in the first direction, the plate-like portion dividing the stacked body in a second direction that crosses both the stacking direction and the first direction, wherein
the plate-like portion includes, in the stepped portion, a plurality of contact portions that is arranged intermittently in the first direction, the plurality of contact portions penetrating the stacked body and connecting with the first conductive layer.
2. The semiconductor memory device according to claim 1 , wherein
the plurality of contact portions is connected in the first direction at an upper position of the plate-like portion in the stepped portion, by the third conductive layer that extends in the first direction so as to divide a part of the plurality of second conductive layers in the second direction.
3. The semiconductor memory device according to claim 2 , wherein
in the stepped portion, the plate-like portion includes, in a lower portion thereof, a second insulating layer that is divided by the plurality of contact portions in the first direction.
4. The semiconductor memory device according to claim 3 , wherein
the second insulating layer is not arranged in a lower portion of the plate-like portion in the memory region, and
the third conductive layer is connected to the first conductive layer in the first direction continuously in the memory region.
5. The semiconductor memory device according to claim 1 , further comprising:
a plurality of second pillars that is arranged in the stepped portion and extends through the stacked body in the stacking direction, wherein
the plurality of contact portions is arranged while being off-aligned with a position opposed in the second direction with each of second pillars lined up in the first direction neighboring the plate-like portion, from among the plurality of second pillars.
6. The semiconductor memory device according to claim 5 , wherein
each of the plurality of contact portions has a width in the second direction, wider than a width of the other portion of the plate-like portion in the second direction.
7. The semiconductor memory device according to claim 5 , wherein
the plurality of first and second pillars is scatteringly arranged in the stacked body, and
an arrangement density of the plurality of second pillars per unit area of the plurality of second conductive layers is lower than an arrangement density of the plurality of first pillars per the unit area.
8. The semiconductor memory device according to claim 7 , wherein
the plurality of first pillars is arranged staggered when viewed in the stacking direction, and
the plurality of second pillars is arranged to form a grid pattern when viewed in the stacking direction.
9. The semiconductor memory device according to claim 1 , wherein
the plate-like portion includes:
a first plate-like portion; and
a second plate-like portion neighboring the first plate-like portion in the second direction, and
the plurality of contact portions includes:
a plurality of first contact portions included in the first plate-like portion; and
a plurality of second contact portions included in the second plate-like portion, and individually arranged while being off-aligned with positions opposed in the second direction with the plurality of first contact portions.
10. The semiconductor memory device according to claim 9 , wherein
a distance between neighboring ones of the plurality of first contact portions is half or shorter than a distance between the first plate-like portion and the second plate-like portion.
11. The semiconductor memory device according to claim 1 , wherein
the plate-like portion includes:
a first plate-like portion; and
a second plate-like portion neighboring the first plate-like portion in the second direction, and
the plurality of contact portions includes:
a plurality of first contact portions included in the first plate-like portion; and
a plurality of second contact portions included in the second plate-like portion, and individually arranged while being aligned in the second direction with the plurality of first contact portions.
12. The semiconductor memory device according to claim 11 , wherein
a distance between neighboring ones of the plurality of first contact portions is quarter or shorter than a distance between the first plate-like portion and the second plate-like portion.
13. A semiconductor memory device comprising:
a first conductive layer;
a stacked body including a plurality of second conductive layers and a plurality of first insulating layers alternately stacked one by one above the first conductive layer, and including a stepped portion in which the plurality of second conductive layers is terraced;
a plurality of first pillars arranged in a memory region that is away from the stepped portion in a first direction that crosses a stacking direction of the stacked body, each first pillar including a semiconductor layer that penetrates the stacked body and connects with the first conductive layer, and forming a memory cell at an intersection with at least a part of the plurality of second conductive layers; and
a plate-like portion that extends in the stacked body from the stepped portion to the memory region continuously in the stacking direction and in the first direction, and divides the stacked body in a second direction that crosses both the stacking direction and the first direction, wherein
the plate-like portion includes:
a sidewall insulating layer covering sidewalls that are opposed each other in the second direction of the plate-like portion; and
a third conductive layer that extends inside the sidewall insulating layer from the stepped portion to the memory region continuously, and is electrically connected to the first conductive layer, and
the sidewall insulating layer includes, in the stepped portion intermittently in the first direction, first portions each having a thickness larger than a thickness of a second portion other than the first portions in a direction that crosses the stacking direction.
14. The semiconductor memory device according to claim 13 , wherein
the sidewall insulating layer contains, in the first portions, a metal element-containing layer that extends in the sidewall insulating layer in the stacking direction, at a predetermined position in a thickness direction of the sidewall insulating layer.
15. The semiconductor memory device according to claim 14 , wherein
the metal element-containing layer is also arranged in the first portions, on a face, opposed to the second conductive layers, of the sidewall insulating layer.
16. The semiconductor memory device according to claim 15 , wherein
the metal element-containing layer is not arranged in the first portions, on a face, opposed to the first insulating layers, of the sidewall insulating layer.
17. The semiconductor memory device according to claim 15 , wherein
the metal element-containing layer is arranged in the second portion, on a face, opposed to the first insulating layers, of the sidewall insulating layer.
18. The semiconductor memory device according to claim 17 , wherein
the metal element-containing layer is not arranged in the second portion, on a face, opposed to the second conductive layers, of the sidewall insulating layer.
19. The semiconductor memory device according to claim 17 , wherein
the plate-like portion has, in the memory region, a layer structure same as that of the plate-like portion in the second portion.
20. The semiconductor memory device according to claim 13 , wherein
the plate-like portion in the second portion has a width in the second direction wider than that in the first portion at least in the stepped portion.