Gate contact structure for a trench power MOSFET with a split gate configuration
An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.
1. An integrated circuit transistor device, comprising:
a semiconductor substrate providing a drain;
a first doped region buried in the semiconductor substrate providing a body;
a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
a trench extending into the semiconductor substrate and passing through the first and second doped regions;
a polyoxide region within the trench;
a polygate region within the trench, said polygate region comprising: a first gate lobe on a first side of the polyoxide region and a second gate lobe on a second side of the polyoxide region opposite said first side;
an insulating layer extending over the first doped region and trench; and
a pair of gate contacts for said trench, said pair of gate contacts comprising:
a first gate contact extending through the insulating layer and into the first gate lobe, wherein the first gate contact has a first length extending parallel to a longitudinal direction of the trench that is greater than a first width perpendicular to the first length; and
a second gate contact extending through the insulating layer and into the second gate lobe, wherein the second gate contact has a second length extending parallel to the longitudinal direction of the trench that is greater than a second width perpendicular to the second length.
2. The integrated circuit transistor device of claim 1 , wherein the first and second gate contacts are in a lateral side-by-side arrangement.
3. The integrated circuit transistor device of claim 1 , wherein the first and second gate contacts are offset from each other in a longitudinal direction of the trench.
4. The integrated circuit transistor device of claim 3 , wherein no cross section through said trench in a plane perpendicular to the longitudinal direction of the trench passes through both the first gate contact and the second gate contact.
5. The integrated circuit transistor device of claim 1 , wherein the polygate region further comprises a bridge region extending over the polyoxide region and electrically coupling the first gate lobe to the second gate lobe.
6. The integrated circuit transistor device of claim 5 , wherein a portion of the bridge region laterally extends between the first and second gate contacts.
7. The integrated circuit transistor device of claim 1 , wherein the polyoxide region includes a void, and wherein each of the first and second gate contacts is offset from the void in a lateral direction of the trench.
8. The integrated circuit transistor device of claim 1 , further comprising a metal layer extending over the insulating layer and electrically connecting the first and second gate contacts.
9. The integrated circuit transistor device of claim 1 , further comprising a gate insulator layer along walls of the trench and positioned between each of the first and second gate lobes and the semiconductor substrate.
10. The integrated circuit transistor device of claim 1 , further comprising a polysource region within said trench, wherein the polysource region is longitudinally aligned with the polyoxide region.
11. The integrated circuit transistor device of claim 10 , wherein said polyoxide region is an oxidized portion of said polysource region.
12. The integrated circuit transistor device of claim 1 , wherein each of the first and second gate contacts comprises a Titanium-Titanium Nitride barrier layer and a Tungsten plug.
13. An integrated circuit transistor, comprising:
a semiconductor substrate providing a drain;
a first doped region buried in the semiconductor substrate providing a body;
a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
a trench extending into the semiconductor substrate and passing through the first and second doped regions;
a polyoxide region within the trench;
a polygate region within the trench, said polygate region comprising: a first gate lobe on a first side of the polyoxide region and a second gate lobe on a second side of the polyoxide region opposite said first side;
an insulating layer extending over the first doped region and trench; and
a pair of gate contacts for said trench, said pair of gate contacts comprising:
a first gate contact extending through the insulating layer and into the first gate lobe; and
a second gate contact extending through the insulating layer and into the second gate lobe;
wherein the polyoxide region is aligned with a center of the trench and wherein a center of each of the first and second gate contact is located between a center of the corresponding first and second gate lobe and the center of the trench and in contact with the polyoxide region.
14. The integrated circuit transistor device of claim 13 , wherein the first and second gate contacts are in a lateral side-by-side arrangement.
15. The integrated circuit transistor device of claim 13 , wherein the first and second gate contacts are offset from each other in a longitudinal direction of the trench.
16. The integrated circuit transistor device of claim 15 , wherein no cross section through said trench in a plane perpendicular to the longitudinal direction of the trench passes through both the first gate contact and the second gate contact.
17. An integrated circuit transistor device, comprising:
a semiconductor substrate providing a drain;
a first doped region buried in the semiconductor substrate providing a body;
a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
a trench extending into the semiconductor substrate and passing through the first and second doped regions;
an insulated polysource region within the trench;
a polyoxide region within the trench and aligned with said insulated polysource region, wherein said polyoxide region includes void;
a first insulated gate lobe on a first side of the polyoxide region;
a second insulated gate lobe on a second side of the polyoxide region opposite said first side;
a first gate contact extending into the first gate lobe, said first gate contact laterally offset from a longitudinal center of the trench such that a depth of the first gate contact does not reach said void; and
a second gate contact extending into the second gate lobe, said second gate contact laterally offset from the longitudinal center of the trench such that a depth of the second gate contact does not reach said void.
18. The integrated circuit transistor device of claim 17 , further comprising an insulating layer extending over the first doped region and trench, wherein said first and second gate contacts extend through the insulating layer and are laterally insulated from each other at a level of the insulating layer by a portion of said insulating layer.
19. The integrated circuit transistor device of claim 17 , wherein the first and second gate contacts are in a lateral side-by-side arrangement.
20. The integrated circuit transistor device of claim 17 , wherein the first and second gate contacts are offset from each other in a longitudinal direction of the trench.
21. The integrated circuit transistor device of claim 18 , further comprising a bridge region extending over the polyoxide region and electrically coupling the first insulated gate lobe to the second insulated gate lobe.
22. The integrated circuit transistor device of claim 21 , wherein the bridge region laterally extends between the first and second gate contacts.
23. The integrated circuit transistor device of claim 17 , wherein said polyoxide region is an oxidized portion of said insulated polysource region.
24. An integrated circuit transistor device, comprising:
a semiconductor substrate providing a drain;
a first doped region buried in the semiconductor substrate providing a body;
a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
a trench extending into the semiconductor substrate and passing through the first and second doped regions;
a polyoxide region within the trench;
a polygate region within the trench, said polygate region comprising: a first gate lobe on a first side of the polyoxide region, a second gate lobe on a second side of the polyoxide region opposite said first side and a bridge region extending over the polyoxide region and electrically coupling the first insulated gate lobe to the second insulated gate lobe;
an insulating layer extending over the first doped region and trench; and
a gate contact extending through the insulating layer and into the first gate lobe for said trench, and wherein said bridge region laterally extends away from said gate contact, wherein the gate contact has a length extending parallel to a longitudinal direction of the trench that is greater than a width perpendicular to the length.
25. An integrated circuit transistor device, comprising:
a semiconductor substrate providing a drain;
a first doped region buried in the semiconductor substrate providing a body;
a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
a trench extending into the semiconductor substrate and passing through the first and second doped regions;
a polyoxide region within the trench;
a polygate region within the trench, said polygate region comprising: a first gate lobe on a first side of the polyoxide region, a second gate lobe on a second side of the polyoxide region opposite said first side and a bridge region extending over the polyoxide region and electrically coupling the first insulated gate lobe to the second insulated gate lobe;
an insulating layer extending over the first doped region and trench; and
a gate contact extending through the insulating layer and into the first gate lobe for said trench, and wherein said bridge region laterally extends away from said gate contact;
wherein the polyoxide region includes a void, and wherein the gate contact is offset from the void in a lateral direction of the trench.