IP Library › Granted Patent US 12,225,512
Granted Patent B2
US 12,225,512 · App. 18/521,846 · Granted Feb 11, 2025

Base station, terminal, and communication method

Inventors: Ayako Horiuchi (Kanagawa, JP); Hidetoshi Suzuki (Kanagawa, JP)
Assignee: Panasonic Intellectual Property Corporation of America
H04W72/044H04W72/23
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Quick Facts
Patent No.
US 12,225,512
App. No.
18/521,846
Granted
Feb 11, 2025
Kind
B2
Abstract

In a base station, a signal allocating unit allocates downlink control signals (DCI) to a control channel region (CORESET) constituted by a plurality of control channel elements (CCEs), and a transmitting unit transmits the downlink control signals. In this case, the number of resource element groups (REGs) that constitute the CCE is a power of 2, and a bundling size indicating the number of REGs included in the REGs that constitute the CCE and arranged in adjacent resource blocks is a power of 2.

Claims (11)

1. An integrated circuit for a base station, the integrated circuit comprising:

at least one output, which, in operation, outputs a signal, and circuitry, which, in operation, controls:

setting a control-resource set (CORESET) in a physical downlink control channel (PDCCH) comprising a control channel element (CCE); and

transmitting a downlink control signal in the CORESET,

wherein the CCE is formed of 6 resource-element groups (REGs) in the CORESET, the 6 REGs being bundled into REG bundles, and

a REG bundle size of the REG bundles is different according to a number of symbols of the CORESET.

2. The integrated circuit according to claim 1 , wherein the number of symbols of the CORESET is indicated by a higher layer signaling.

3. The integrated circuit according to claim 1 , wherein the number of symbols of the CORESET is a time duration of the CORESET.

4. The integrated circuit according to claim 1 , wherein in a case that the number of symbols of the CORESET is 2 or 3, the CCE is arranged over a plurality of symbols of the CORESET.

5. The integrated circuit according to claim 1 , wherein a common demodulation reference signal (DMRS) is used for each of REG bundles.

6. The integrated circuit according to claim 1 , wherein REGs included in each of the REG bundles are adjacent to each other.

Priority Claims (1)
JP 2017-052867 · Mar 17, 2017 · national
Continuity (4)
Continuation 18063631 · Dec 8, 2022
Continuation 17195983 · Mar 9, 2021
Continuation 16479212
Related Publication 20240098710A1 · Mar 21, 2024
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