Communication unit, integrated circuits and method for clock and data synchronization
A communication unit includes a plurality of cascaded devices that include at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device and at least one slave device each include: a demodulator circuit configured to receive a distributed reference clock signal and re-create a system clock signal therefrom; a clock generation circuit that includes an internally-generated reference phase locked loop configured to receive the re-created system clock signal to create a master-slave clock signal; and an analog-to-digital converter, ADC, coupled to the reference phase locked loop and configured to use a same master-slave clock signal to align respective sampling instants between each ADC of the at least one master device and at least one slave device.
1. A radar unit comprising:
a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement, wherein the at least one slave device and the at least one master device are connected through transmission lines, and wherein the at least one master device and at least one slave device each include:
a demodulator circuit configured to receive a distributed reference clock signal that includes a system clock signal and a chirp start signal embedded in the system clock signal, and to produce a re-created system clock signal and a reproduced chirp start signal from the distributed reference clock signal;
a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal, and to create a master-slave clock signal based on the re-created system clock signal; and
an analog-to-digital converter, ADC, coupled to the reference phase locked loop and configured to use the master-slave clock signal and the reproduced chirp start signal to align respective sampling instants of a received representation of an echo signal, resulting from a transmitted frequency modulated signal, between each ADC of the at least one master device and at least one slave device.
2. The radar unit of claim 1 wherein the distributed reference clock signal is received over a low voltage differential signalling, LVDS, link.
3. The radar unit of claim 1 wherein the internally-generated reference phase locked loop is an internally-generated reference charge pump analog-to-digital converter phase locked loop, CPADCPLL, that is turned on in each of the at least one master device and at least one slave device.
4. The radar unit of claim 3 wherein the internally-generated reference CPADCPLL is configured to provide an ADC clock signal to the ADCs that is higher than the received distributed clock signal and that includes respective time-aligned sampling instants between each ADC of each of the at least one master device and at least one slave device.
5. The radar unit of claim 1 , wherein at least one of the at least one master device and at least one slave device further comprises:
a digital controller coupled to the demodulator circuit and configured to re-sample the re-created system clock signal.
6. The radar unit of claim 1 , wherein the demodulator circuit is configured to receive the distributed reference clock signal that includes the chirp start signal, and to de-embed the chirp start signal from the distributed reference clock signal to produce the re-created system clock signal.
7. The radar unit of claim 3 , wherein the clock generation circuit is operably coupled to a Mobile Industry Processor Interface, MIPI, and the internally-generated reference CPADCPLL is configured to provide a clock signal to the MIPI in each of the at least one master device and at least one slave device that has a higher frequency than the distributed reference clock signal.
8. The radar unit of claim 1 , wherein the demodulator circuit is terminated by a differential resistor.
9. A method for clock distribution and synchronization in a radar unit having at least one master device and at least one slave device configured in a master-slave arrangement, wherein the at least one slave device and the at least one master device are connected through transmission lines, wherein the method includes, at each of the at least one master device and at least one slave device, performing steps of:
receiving a distributed reference clock signal, wherein the distributed reference clock signal includes a system clock signal modulated with a chirp start signal;
producing a re-created system clock signal and a reproduced chirp start signal from the distributed reference clock signal;
receiving the re-created system clock signal at an internally-generated reference phase locked loop, and creating a master-slave clock signal based on the re-created system clock signal; and
using the re-created master-slave clock signal and the reproduced chirp start signal at an analog-to-digital converter, ADC, to align respective sampling instants of a received representation of an echo signal, resulting from a transmitted frequency modulated signal, between each ADC of the at least one master device and at least one slave device.
10. The radar unit of claim 1 , wherein lengths of connections between each of the at least one slave device and the at least one master device are equal.
11. The radar unit of claim 1 , wherein the at least one slave device and the at least one master device are coupled to a star routed printed circuit board.
12. The method for clock distribution and synchronization of claim 9 , wherein lengths of connections between each of the at least one slave device and the at least one master device are equal.
13. The method for clock distribution and synchronization of claim 9 , wherein the at least one slave device and the at least one master device are star routed.
14. The radar unit of claim 1 , wherein:
the at least one master device is configured to embed the chirp start signal in the system clock signal using amplitude modulation; and
the demodulator circuit is configured to produce the reproduced chirp start signal from the distributed master-slave clock signal using amplitude demodulation.
15. The radar unit of claim 1 , wherein the transmitted frequency modulated signal is a frequency-modulated continuous wave (FMCW) radar signal.
16. A radar unit comprising:
a master device configured to
transmit a chirp signal based on a chirp start signal,
produce a modulated embedded master-slave clock signal that includes a system clock signal modulated by the chirp start signal,
distribute the modulated embedded master-slave clock signal, as a distributed system clock signal, to the master device and to a slave device,
receive the distributed system clock signal,
produce a re-created system clock signal and a reproduced chirp start signal from the distributed system clock signal,
receive a first echo signal resulting from the transmitted chirp signal, and
sample a representation of the first echo signal, wherein sampling instants of the representation of the first echo signal are aligned based on the re-created system clock signal and the reproduced chirp start signal; and
the slave device coupled to the master device in a master-slave arrangement, wherein the slave device is configured to
receive the distributed system clock signal,
produce the re-created system clock signal and the reproduced chirp start signal from the distributed system clock signal,
receive a second echo signal resulting from the transmitted chirp signal, and
sample a representation of the second echo signal, wherein sampling instants of the representation of the second echo signal are aligned based on the re-created system clock signal and the reproduced chirp start signal.
17. The radar unit of claim 16 , wherein the chirp signal is a frequency-modulated continuous wave (FMCW) radar signal.
18. The radar unit of claim 16 , wherein the master device and the slave device are coupled to a star routed printed circuit board.