IP Library › Granted Patent US 12,229,402
Granted Patent B2
US 12,229,402 · App. 17/897,014 · Granted Feb 18, 2025

Intelligent operation scheduling based on latency of operations

Inventors: John D. Davis (San Francisco, CA); John Hayes (Mountain View, CA); Hari Kannan (Sunnyvale, CA); Nenad Miladinovic (Los Gatos, CA); Zhangxi Tan (Mountain View, CA)
Assignee: PURE STORAGE, INC.
G06F3/0604G06F3/0619G06F3/064G06F3/0659G06F3/067G06F3/0688G06F11/1008G06F11/1068G11C29/52H03M13/154H03M13/373H03M13/1102H03M13/1515H03M13/3761
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Quick Facts
Patent No.
US 12,229,402
App. No.
17/897,014
Granted
Feb 18, 2025
Kind
B2
Abstract

A storage system is provided. The storage system includes a plurality of non-volatile memory units and a processor operatively coupled to a plurality of non-volatile memory units. The processor is to perform a method including receiving a request to read data from the storage system. The method also includes determining whether a storage operation should be delayed, based on the request to read the data from the storage system. The method further includes in response to determining that the storage operation should be delayed, delaying the storage operation. The method further includes performing a read operation for the request to read the data.

Claims (43)

1. A method, comprising:

receiving a request to read data from a storage system;

determining whether one of an interruptible write operation or an interruptible erase operation being performed on flash memory of the storage system should be paused based at least in part on the request to read the data from the storage system having a lower latency than the one of the interruptible write operation or the interruptible erase operation;

in response to determining that the storage operation should be paused, pausing the one of the interruptible write operation or the interruptible erase operation; and

performing a read operation for the request to read the data.

2. The method of claim 1 , wherein determining whether the one of the interruptible write operation or the interruptible erase operation should be paused comprises:

determining whether delaying the one of the interruptible write operation or the interruptible erase operation exceeds a latency limit for the storage operation.

3. The method of claim 1 , wherein determining whether the one of the interruptible write operation or the interruptible erase operation should be paused comprises:

determining a priority of the read operation; and

determining whether the one of the interruptible write operation or the interruptible erase operation should be paused based on the priority of the read operation.

4. The method of claim 1 , further comprising:

in response to determining that the one of the interruptible write operation or the interruptible erase operation should not be paused, allowing the one of the interruptible write operation or the interruptible erase operation to proceed.

5. A storage system, comprising:

a plurality of non-volatile memory units comprising flash memory; and

a processor operatively coupled to a plurality of non-volatile memory units, the processor configured to:

receive a request to read data from the storage system;

determine whether one of an interruptible write operation or an interruptible erase operation being performed on the flash memory should be paused based at least in part on the request to read the data from the storage system having a lower latency than the one of the interruptible write operation or the interruptible erase operation;

in response to determining that the storage operation should be paused, pause the one of the interruptible write operation or the interruptible erase operation; and

perform a read operation for the request to read the data.

6. The storage system of claim 5 , wherein to determine whether the one of the interruptible write operation or the interruptible erase operation should be paused, the processor is further configured to:

determine whether delaying the one of the interruptible write operation or the interruptible erase operation exceeds a latency limit for the one of the interruptible write operation or the interruptible erase operation.

7. The storage system of claim 5 , wherein to determine whether the one of the interruptible write operation or the interruptible erase operation should be paused, the processor is further configured to:

determine a priority of the read operation; and

determine whether the one of the interruptible write operation or the interruptible erase operation should be paused based on the priority of the read operation.

8. The storage system of claim 5 , wherein the processor is further configured to:

in response to determining that the one of the interruptible write operation or the interruptible erase operation should not be paused, allow the one of the interruptible write operation or the interruptible erase operation to proceed.

9. A non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to:

receive a request to read data from a storage system;

determine whether one of the interruptible write operation or the interruptible erase operation should be paused based at least in part on the request to read the data from the storage system having a lower latency than the one of the interruptible write operation or the interruptible erase operation;

in response to determining that the one of the interruptible write operation or the interruptible erase operation should be paused, pause the one of the interruptible write operation or the interruptible erase operation; and

perform a read operation for the request to read the data.

10. The non-transitory, computer-readable media of claim 9 , wherein to determine whether the one of the interruptible write operation or the interruptible erase operation should be paused, the processor is further to:

determine whether delaying the one of the interruptible write operation or the interruptible erase operation exceeds a latency limit for the one of the interruptible write operation or the interruptible erase operation.

11. The non-transitory, computer-readable media of claim 9 , wherein to determine whether the one of the interruptible write operation or the interruptible erase operation should be paused, the processor is further to:

determine a priority of the read operation; and

determine whether the one of the interruptible write operation or the interruptible erase operation should be paused based on the priority of the read operation.

12. The non-transitory, computer-readable media of claim 9 , wherein the processor is further to:

in response to determining that the one of the interruptible write operation or the interruptible erase operation should not be paused, allow the one of the interruptible write operation or the interruptible erase operation to proceed.

13. The method of claim 1 , wherein the interruptible write is performed using a quad-level cell (QLC) programming mode.

14. The method of claim 1 , wherein determining whether the one of the interruptible write operation or the interruptible erase operation should be paused further comprises:

determining whether pausing the interruptible erase operation causes the storage system to run out of storage capacity; and

in response to determining that pausing the interruptible erase operation causes the storage system to run out of the storage capacity, allow the interruptible erase operation to proceed.

15. The method of claim 1 , wherein the storage system comprises a plurality of solid-state storage devices comprising the flash memory.

Continuity (5)
Continuation 17213697 · Mar 26, 2021
Continuation 16278547 · Feb 18, 2019
Continuation 15285410 · Oct 4, 2016
Continuation 14454503 · Aug 7, 2014
Related Publication 20220404970A1 · Dec 22, 2022
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