Flash memory controller and memory device for accessing flash memory module, and associated method
A method for accessing a flash memory module includes: sequentially writing Nth-(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively, where the Nth-(N+K)th ECCs are used to correct errors of the Nth-(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth-(N+K)th ECCs to generate the (N+K+1)th ECC.
1. A method for accessing a flash memory module, wherein the flash memory module is a 3D flash memory module, and the method comprises:
sequentially writing Nth-(N+K)th data to floating gate transistors of different word line groups of each of a plurality of flash memory chips of the flash memory module, wherein each of the word line groups comprises a plurality of word lines, and encoding the Nth-(N+K)th data to generate Nth-(N+K)th error correction codes (ECCs), respectively, where the Nth-(N+K)th ECCs are used to correct errors of the Nth-(N+K)th data, respectively, and N and K are positive integers;
writing (N+K+1)th data to floating gate transistors of another word line group of each of the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth-(N+K)th ECCs, to generate (N+K+1)th ECC;
writing the (N+K+1)th ECC, or writing the (N+K)th ECC and (N+K+1)th ECC, to a specific block of the flash memory module that is different from block(s) storing the Nth-(N+K+1)th data, and deleting the Nth-(N+K−1)th ECCs from the 3D flash memory module;
reading specific data from the block(s) of the flash memory module, wherein the specific data is not the (N+K)th data or the (N+K+1)th data; and
when an error that is uncorrectable when reading the specific data, reading the (N+K+1)th ECC stored in the specific block, or reading the (N+K)th and the (N+K+1)th ECC stored in the specific block, to perform error correction upon the specific data.
2. The method of claim 1 , wherein K is 1, and the step of generating the (N+K+1)th ECC comprises:
encoding the (N+K)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.
3. The method of claim 1 , wherein K is 1, and the step of generating the (N+K+1)th ECC comprises:
encoding the Nth ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.
4. The method of claim 1 , wherein K is an integer within 1-M, and the Nth data is written to a first page of a super block of the plurality of flash memory chips, wherein the super block comprises a block of each flash memory chip of the plurality of flash memory chips; and the (N+M+1)th data is written to a last page of the super block of the plurality of flash memory chips.
5. The method of claim 4 , wherein the step of generating the (N+K+1)th ECC comprises
encoding the (N+K)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.
6. The method of claim 4 , wherein the step of generating the (N+K+1)th ECC comprises:
encoding the (N+K−1)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.
7. The method of claim 1 , wherein the specific block is a single-level cell (SLC) block.
8. The method of claim 1 , wherein K is an integer within 1−M, and the Nth data is written to a first page of a super block of the plurality of flash memory chips, wherein the super block comprise a block of each flash memory chip of the plurality of flash memory chips; and the (N+M+1)th data is written to a last page of the super block of the plurality of flash memory chips.
9. A flash memory controller, arranged to access a flash memory module, wherein the flash memory module is a 3D flash memory module, and the flash memory controller comprises:
a memory, arranged to store a program code;
a microprocessor, arranged to execute the program code, to control access of the flash memory module; and
an encoder;
wherein the microprocessor sequentially writes the Nth-(N+K)th data to floating gate transistors of different word line groups of each of a plurality of flash memory chips in the flash memory module, respectively, wherein each of the word line groups comprises a plurality of word lines, and the encoder encodes the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively, the Nth-(N+K)th ECCs are arranged to perform error correction upon the Nth-(N+K)th data written to the plurality of flash memory chips, and N and K are positive integers; and the microprocessor writes (N+K+1)th data to floating gate transistors of another word line group of each of the plurality of flash memory chips of the flash memory module, and the encoder encodes at least one of the Nth-(N+K)th ECCs together with the (N+K+1)th data, to generate (N+K+1)th ECC; and the microprocessor writes the (N+K+1)th ECC, or writes the (N+K)th ECC and (N+K+1)th ECC, to a specific block of the flash memory module that is different from block(s) storing the Nth-(N+K+1)th data, and deletes the Nth-(N+K−1)th ECCs from the 3D flash memory module; the microprocessor further reads specific data from the block(s) of the flash memory module, wherein the specific data is not the (N+K)th data or the (N+K+1)th data; and when an error that is uncorrectable when reading the specific data, the microprocessor reads the (N+K+1)th ECC stored in the specific block, or reads the (N+K)th and the (N+K+1)th ECC stored in the specific block, to perform error correction upon the specific data.
10. The flash memory controller of claim 9 , wherein K is 1, and the encoder encodes the (N+K)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.
11. The flash memory controller of claim 9 , wherein K is 1, and the encoder encodes the Nth ECC together with the (N+K+1)th data to generate (N+K+1)th ECC.
12. The flash memory controller of claim 9 , wherein K is an integer within 1−M, and the Nth data is written to a first page of a super block of the plurality of flash memory chips, wherein the super block comprises a block of each flash memory chip within the plurality of flash memory chips; and the (N+M+1)th data is written to a last page of the super block of the plurality of flash memory chips.
13. The flash memory controller of claim 12 , wherein the encoder encodes the (N+K)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.
14. The flash memory controller of claim 12 , wherein the encoder encodes the (N+K−1)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.
15. The flash memory controller of claim 9 , wherein the specific block is a single-level cell (SLC) block.
16. The flash memory controller of claim 9 , wherein K is an integer within 1−M, and the Nth data is written to a first page of a super block of the plurality of flash memory chips, wherein the super block comprises a block of each flash memory chip within the plurality of flash memory chips; and the (N+M+1)th data is written to a last page of the super block of the plurality of flash memory chips.
17. A memory apparatus, comprising:
a flash memory module, wherein the flash memory module is a 3D flash memory module; and
a flash memory controller, arranged to access the flash memory module;
wherein the flash memory controller sequentially writes Nth-(N+K)th data to floating gate transistors of different word line groups of each of a plurality of flash memory chips in the flash memory module, respectively, wherein each of the word line groups comprises a plurality of word lines, and encodes the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively; the Nth-(N+K)th ECCs are arranged to perform error correction upon the Nth-(N+K)th data written to the plurality of flash memory chips, and N and K are positive integers; and the flash memory controller writes (N+K+1)th data to floating gate transistors of another word line group of each of the plurality of flash memory chips in the flash memory module, and encodes at least one of the Nth-(N+K)th ECCs together with the (N+K+1)th data, to generate (N+K+1)th ECC; and the flash memory controller writes the (N+K+1)th ECC, or writes the (N+K)th ECC and (N+K+1)th ECC, to a specific block of the flash memory module that is different from block(s) storing the Nth-(N+K+1)th data, and deletes the Nth-(N+K−1)th ECCs from the 3D flash memory module; the flash memory controller further reads specific data from the block(s) of the flash memory module, wherein the specific data is not the (N+K)th data or the (N+K+1)th data; and when an error that is uncorrectable when reading the specific data, the flash memory controller reads the (N+K+1)th ECC stored in the specific block, or reads the (N+K)th and the (N+K+1)th ECC stored in the specific block, to perform error correction upon the specific data.
18. The memory apparatus of claim 17 , wherein the flash memory controller writes the Nth-(N+K+1)th data to a plurality of blocks of the plurality of flash memory chips, and the plurality of blocks are multiple-level cell (MLC) blocks, triple-level cell (TLC) blocks, or quad-level cell (QLC) blocks; and the flash memory controller writes the Nth-(N+K+1)th ECCs to at least one specific block of the flash memory module, wherein the specific block is an SLC block.