IP Library Granted Patent US 12,499,043
Granted Patent B2
US 12,499,043 · App. 18/818,308 · Granted Dec 16, 2025

Writing data to a solid state storage array to accommodate power failure

Inventors: Gordon James Coleman (Los Altos, CA); Eric Seppanen (Mountain View, CA)
Assignee: PURE STORAGE, INC.
G06F12/0246G06F3/061G06F3/064G06F3/0647G06F3/0656G06F3/067G06F2212/7201G06F2212/7202G06F2212/7209
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,499,043
App. No.
18/818,308
Granted
Dec 16, 2025
Kind
B2
Abstract

A storage array controller may receive a write request comprising data to be stored at one or more solid-state storage devices. A write granularity associated with the write request may be generated that is less than a logical block size associated with the storage array controller. The data associated with the write request may be segmented based on the generated write granularity. The write request may be executed to store the segmented data at the one or more solid-state storage devices.

Claims (28)

1 . A system comprising:

a solid-state storage array comprising a plurality of solid-state storage devices; and

a storage controller coupled to the solid-state storage array, the storage controller comprising a processing device, the processing device configured to:

execute a write request associated with a first portion of data and a second portion of data, wherein execution of the write request comprises storing the first portion of the data at the one or more of the plurality of solid-state storage devices and storing the second portion of the data at a buffer; and

responsive to identifying that a triggering condition has occurred, selecting a memory location for transferring the second portion of the data from the buffer, wherein the selecting is based on an amount of energy required for the transferring.

2 . The system of claim 1 , wherein the triggering condition comprises a loss of power.

3 . The system of claim 1 , wherein the memory location comprises a non volatile random access memory (NVRAM) that is external to the plurality of solid-state storage devices.

4 . The system of claim 1 , wherein the memory location comprises the one or more of the plurality of solid-state storage devices.

5 . The system of claim 4 , wherein the memory location is a single-level cell (SLC) memory of the one or more of the plurality of solid-state storage devices.

6 . The system of claim 4 , wherein the memory location is a quad-level cell (QLC) memory of the one or more of the plurality of solid-state storage devices.

7 . The system of claim 1 , wherein the selecting is between one of a quad-level cell (QLC) memory and a single level cell (SLC) memory of the one or more of the plurality of solid-state storage devices.

8 . The system of claim 7 , wherein after the triggering condition, the amount of energy is supplied by a capacitor of the system.

9 . A method comprising:

execute a write request associated with a first portion of data and a second portion of data, wherein the executing the write request comprises storing the first portion at the one or more of the plurality of solid-state storage devices and storing the second portion of the data at a buffer; and

responsive to identifying that a triggering condition has occurred, selecting a memory location for transferring the second portion of the data from the buffer, wherein the selecting is based on an amount of energy required for the transferring.

10 . The method of claim 9 , wherein the triggering condition comprises a loss of power.

11 . The method of claim 9 , wherein the memory location comprises a non volatile random access memory (NVRAM) that is external to the plurality of solid-state storage devices.

12 . The method of claim 9 , wherein the memory location comprises the one or more of the plurality of solid-state storage devices.

13 . The method of claim 12 , wherein the memory location is a single-level cell (SLC) memory of the one or more of the plurality of solid-state storage devices.

14 . The method of claim 12 , wherein the memory location is a quad-level cell (QLC) memory of the one or more of the plurality of solid-state storage devices.

15 . The method of claim 9 , wherein the selecting is between one of a quad-level cell (QLC) memory and a single level cell (SLC) memory of the one or more of the plurality of solid-state storage devices.

16 . A non-transitory computer readable storage medium storing instructions, which when executed, cause a processing device to:

execute a write request associated with a first portion of data and a second portion of data, wherein the executing the write request comprises storing the first portion at the one or more of the plurality of solid-state storage devices and storing the second portion of the data at a buffer; and

responsive to identifying that a triggering condition has occurred, selecting a memory location for transferring the second portion of the data from the buffer, wherein the selecting is based on an amount of energy required for the transferring.

17 . The non-transitory computer readable storage medium of claim 16 , wherein the triggering condition comprises a loss of power.

18 . The non-transitory computer readable storage medium of claim 16 , wherein the memory location comprises a non volatile random access memory (NVRAM) that is external to the plurality of solid-state storage devices.

19 . The non-transitory computer readable storage medium of claim 16 , wherein the memory location comprises the one or more of the plurality of solid-state storage devices.

20 . The non-transitory computer readable storage medium of claim 16 , wherein the selecting is between one of a quad-level cell (QLC) memory and a single level cell (SLC) memory of the one or more of the plurality of solid-state storage devices.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2024
From: COLEMAN, GORDON JAMES; SEPPANEN, ERIC
To: PURE STORAGE, INC.
Reel/Frame 068451/0511 →
Continuity (6)
Continuation 18360369 · Jul 27, 2023
Continuation 17668940 · Feb 10, 2022
Continuation 17114365 · Dec 7, 2020
Continuation 16186142 · Nov 9, 2018
Provisional Application 62587643 · Nov 17, 2017
Related Publication 20240419587A1 · Dec 19, 2024
References Cited (33)
US 7584335B2 · Daniels · 2009 [cited by examiner]
US 8074021B1 · Miller et al. · 2011 [cited by applicant]
US 8285927B2 · Flynn et al. · 2012 [cited by applicant]
US 8463991B2 · Colgrove et al. · 2013 [cited by applicant]
US 9275063B1 · Natanzon · 2016 [cited by applicant]
US 9304908B1 · Karamcheti · 2016 [cited by examiner]
US 9519594B2 · Flynn et al. · 2016 [cited by applicant]
US 9594633B2 · Colgrove et al. · 2017 [cited by applicant]
US 9858015B2 · Franceschini et al. · 2018 [cited by applicant]
US 9910742B1 · Faibish et al. · 2018 [cited by applicant]
US 10089174B2 · Yang · 2018 [cited by examiner]
US 10185495B2 · Katsuki · 2019 [cited by applicant]
US 10860475B1 · Coleman · 2020 [cited by examiner]
US 11036596B1 · Coleman et al. · 2021 [cited by applicant]
US 11194473B1 · Zhao et al. · 2021 [cited by applicant]
US 11275681B1 · Coleman et al. · 2022 [cited by applicant]
US 20080313364A1 · Flynn et al. · 2008 [cited by applicant]
US 20100180151A1 · Jibbe et al. · 2010 [cited by applicant]
US 20120066435A1 · Colgrove et al. · 2012 [cited by applicant]
US 20120166749A1 · Eleftheriou et al. · 2012 [cited by applicant]
US 20120254508A1 · Walls · 2012 [cited by applicant]
US 20120260150A1 · Cideciyan et al. · 2012 [cited by applicant]
US 20160142485A1 · Mitkar et al. · 2016 [cited by applicant]
US 20170155713A1 · Powell et al. · 2017 [cited by applicant]
US 20180074748A1 · Makin et al. · 2018 [cited by applicant]
US 20180081562A1 · Vasudevan · 2018 [cited by applicant]
US 20180239702A1 · Farmahini Farahani · 2018 [cited by examiner]
US 20200379899A1 · Gole · 2020 [cited by applicant]
US 20220156114A1 · Nagpal et al. · 2022 [cited by applicant]
US 20220164281A1 · Coleman et al. · 2022 [cited by applicant]
US 20240118829A1 · Oh et al. · 2024 [cited by applicant]
US 20250176834A1 · Connor · 2025 [cited by examiner]
Frakes Dan, Up close with Mountain Lion: Power Nap (Frakes, Dan, Working Mac—Up close with Mountain Lion: Power Nap, Macworld.com, Aug. 1, 2012, pp. 1-6. [cited by applicant]