IP Library › Granted Patent US 12,236,117
Granted Patent B2
US 12,236,117 · App. 18/460,269 · Granted Feb 25, 2025

Resiliency management in a storage system

Inventors: Hari Kannan (Sunnyvale, CA); Gordon James Coleman (Los Altos, CA); Yijie Zhao (Milpitas, CA); Peter E. Kirkpatrick (Los Altos, CA); Robert Lee (Pebble Beach, CA); Yuhong Mao (Fremont, CA); Boris Feigin (San Francisco, CA)
Assignee: PURE STORAGE, INC.
G06F3/064G06F3/0604G06F3/0683G06F11/3495
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Quick Facts
Patent No.
US 12,236,117
App. No.
18/460,269
Granted
Feb 25, 2025
Kind
B2
Abstract

One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.

Claims (39)

1. A system comprising:

a plurality of storage devices; and

a storage controller operatively coupled to the plurality of storage devices, the storage controller comprising a processing device, the processing device configured to:

receive one or more performance parameters associated with data storage at a storage device of the plurality of storage devices;

associate a first number of blocks of the storage device to a first portion of the storage device that uses a first programming mode and a second number of blocks of the storage device to a second portion of the storage device that uses a second programming mode based on the one or more performance parameters;

receive a modification to the one or more performance parameters; and

adjust the first number of blocks associated to the first portion and the second number of blocks associated with the second portion based on the modification to the one or more performance parameters.

2. The system of claim 1 , wherein the first programming mode is a single-level cell (SLC) mode and the second programming mode is a multi-level cell (MLC) mode.

3. The system of claim 1 , wherein the first portion of the storage device has a higher resiliency than the second portion of the storage device.

4. The system of claim 3 , wherein the modification to the one or more performance parameters comprises an increase in storage capacity of the system and wherein to adjust the first number of blocks associated to the first portion and the second number of blocks associated with the second portion based on the modification to the one or more performance parameters, the processing device is further configured to:

decrease the first number of blocks associated to the first portion and increase the second number of blocks associated with the second portion.

5. The system of claim 3 , wherein the modification to the one or more performance parameters comprises an increase in performance of the system and wherein to adjust the first number of blocks associated to the first portion and the second number of blocks associated with the second portion based on the modification to the one or more performance parameters, the processing device is further configured to:

increase the first number of blocks associated to the first portion and decrease the second number of blocks associated with the second portion.

6. The system of claim 1 , wherein the one or more performance parameters associated with data stored at the storage device of the plurality of storage devices comprises a storage capacity of the system.

7. The system of claim 1 , wherein the one or more performance parameters associated with data stored at the storage device of the plurality of storage devices comprises a read/write latency of storage system operations performed by the system.

8. The system of claim 1 , wherein the processing device is further to:

allocate one or more blocks of the storage device to the first portion of the storage device upon determining that a number of program/erase cycles to program data to the one or more blocks exceeds a threshold.

9. The system of claim 1 , wherein the processing device is further to:

rotate which blocks of the storage device are allocated to the first portion and the second portion based on a number of program/erase cycles performed on each of the blocks.

10. A method, comprising:

receiving one or more performance parameters associated with data storage at a storage device of a plurality of storage devices;

associating a first number of blocks of the storage device to a first portion of the storage device that uses a first programming mode and a second number of blocks of the storage device to a second portion of the storage device that uses a second programming mode based on the one or more performance parameters;

receiving a modification to the one or more performance parameters; and

adjusting the first number of blocks associated to the first portion and the second number of blocks associated with the second portion based on the modification to the one or more performance parameters.

11. The method of claim 10 , wherein the first programming mode is a single-level cell (SLC) mode and the second programming mode is a multi-level cell (MLC) mode.

12. The method of claim 10 , wherein the first portion of the storage device has a higher resiliency than the second portion of the storage device.

13. The method of claim 10 , wherein the one or more performance parameters associated with data stored at the storage device of the plurality of storage devices comprises a storage capacity of the plurality of storage devices.

14. The method of claim 10 , wherein the one or more performance parameters associated with data stored at the storage device of the plurality of storage devices comprises data resiliency for data stored at the storage device.

15. The method of claim 10 , further comprising:

allocating one or more blocks of the storage device to the first portion of the storage device upon determining that a number of program/erase cycles to program data to the one or more blocks exceeds a threshold.

16. The method of claim 10 , further comprising:

rotating which blocks of the storage device are allocated to the first portion and the second portion based on a number of program/erase cycles performed on each of the blocks.

17. A non-transitory computer readable storage medium storing instructions, which when executed, cause a processing device of a storage controller configured to:

receive one or more performance parameters associated with data storage at a storage device of a plurality of storage devices;

associate a first number of blocks of the storage device to a first portion of the storage device that uses a first programming mode and a second number of blocks of the storage device to a second portion of the storage device that uses a second programming mode based on the one or more parameters;

receive a modification to the one or more performance parameters; and

adjust the first number of blocks associated to the first portion and the second number of blocks associated with the second portion based on the modification to the one or more performance parameters.

18. The non-transitory computer readable storage medium of claim 17 , wherein the first portion of the storage device has a higher resiliency than the second portion of the storage device.

19. The non-transitory computer readable storage medium of claim 17 , wherein the one or more performance parameters associated with data stored at the storage device of the plurality of storage devices comprises a storage capacity of the plurality of storage devices.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2024
From: KANNAN, HARI; COLEMAN, GORDON JAMES; ZHAO, YIJIE; KIRKPATRICK, PETER E.; LEE, ROBERT; MAO, YUHONG; FEIGIN, BORIS
To: PURE STORAGE, INC.
Reel/Frame 067076/0169 →
Continuity (3)
Continuation 17955493 · Sep 28, 2022
Continuation 17124851 · Dec 17, 2020
Related Publication 20230418496A1 · Dec 28, 2023
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