On-chip atomic transaction engine
A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.
1. A method, comprising:
receiving, at a local atomic transaction engine, information describing an atomic transaction to be performed at a plurality of different memory addresses of a distributed shared memory, wherein individual portions of the distributed shared memory are controlled by a plurality of atomic transaction engines including the local atomic transaction engine and a plurality of remote atomic transaction engines; and
sending, responsive to the receiving, the information describing the atomic transaction to one or more of the plurality of remote atomic transaction engines to be performed at respective memory addresses of the plurality of different memory addresses controlled by the one or more of the plurality of remote atomic transaction engines.
2. The method of claim 1 , wherein the information describing the atomic transaction to be performed at the plurality of different memory addresses is received from a processor coupled to the local atomic transaction engine responsive to determining that an operation to be executed by the processor targets the plurality of different memory addresses in the distributed shared memory.
3. The method of claim 1 , further comprising:
causing performance of a portion of the atomic transaction by the local atomic transaction engine responsive to determining that a memory address of the plurality of different memory addresses of the distributed shared memory is controlled by the local atomic transaction engine.
4. The method of claim 3 , wherein causing performance of the portion of the atomic transaction by the local atomic transaction engine comprises:
performing the portion of the atomic transaction by the local atomic transaction engine responsive to determining that the portion of the atomic transaction is performable by circuitry within the local atomic transaction engine without intervention by a processor coupled to the local atomic transaction engine; and
initiating, by the local atomic transaction engine, performance of the portion of the atomic transaction by the processor responsive to determining that the atomic transaction is not performable by circuitry within the local atomic transaction engine without intervention by the processor.
5. The method of claim 4 , wherein initiating, by the local atomic transaction engine, performance of the portion of the atomic transaction by the processor comprises:
writing the information describing the portion of the atomic transaction into one or more storage locations that are accessible to the processor; and
issuing an interrupt to the processor indicating that the atomic transaction should be executed by the processor.
6. The method of claim 1 , further comprising:
receiving, by the local atomic transaction engine from the one or more of the plurality of remote atomic transaction engines, respective response data for the request, and in response to the receiving:
returning, by the local atomic transaction engine, the respective response data to a processor coupled to the local atomic transaction engine; or
writing, by the local atomic transaction engine, the respective response data to a location in memory from which the processor expects to retrieve it.
7. The method of claim 1 , wherein the local atomic transaction engine and the plurality of remote atomic transaction engines communicate other over a dedicated low-latency interconnect.
8. An apparatus, comprising:
a local transaction engine coupled to a processor and memory, wherein the memory implements a portion of a distributed shared memory, and wherein the local atomic transaction engine is configured to:
receive information describing an atomic transaction to be performed at a plurality of different memory addresses of a distributed shared memory, wherein individual portions of the distributed shared memory are controlled by a plurality of atomic transaction engines including the local atomic transaction engine and a plurality of remote atomic transaction engines; and
send, responsive to the receiving, the information describing the atomic transaction to one or more of the plurality of remote atomic transaction engines to be performed at respective memory addresses of the plurality of different memory addresses controlled by the one or more of the plurality of remote atomic transaction engines.
9. The apparatus of claim 8 , wherein the information describing the atomic transaction to be performed at the plurality of different memory addresses is received from a processor coupled to the local atomic transaction engine responsive to determining that an operation to be executed by the processor targets the plurality of different memory addresses in the distributed shared memory.
10. The apparatus of claim 8 , wherein the local atomic transaction engine is further configured to:
cause performance of a portion of the atomic transaction by the local atomic transaction engine responsive to determining that a memory address of the plurality of different memory addresses of the distributed shared memory is controlled by the local atomic transaction engine.
11. The apparatus of claim 10 , wherein to cause performance of the portion of the atomic transaction, the local atomic transaction engine is configured to:
perform the portion of the atomic transaction by the local atomic transaction engine responsive to determining that the portion of the atomic transaction is performable by circuitry within the local atomic transaction engine without intervention by a processor coupled to the local atomic transaction engine; and
initiate performance of the portion of the atomic transaction by the processor responsive to determining that the atomic transaction is not performable by circuitry within the local atomic transaction engine without intervention by the processor.
12. The apparatus of claim 11 , wherein to initiate performance of the portion of the atomic transaction by the processor, the local atomic transaction engine is configured to:
write the information describing the portion of the atomic transaction into one or more storage locations that are accessible to the processor; and
issue an interrupt to the processor indicating that the atomic transaction should be executed by the processor.
13. The apparatus of claim 12 , wherein the local atomic transaction engine and the plurality of remote atomic transaction engines communicate other over a dedicated low-latency interconnect.
14. A system, comprising:
a plurality of atomic transaction engines respectively coupled to respective processors and respective memories, wherein the respective memories collectively implement a distributed shared memory, and wherein a local atomic transaction engine of the plurality of atomic transaction engines is configured to:
receive information describing an atomic transaction to be performed at a plurality of different memory addresses of a distributed shared memory, wherein individual portions of the distributed shared memory are controlled by a plurality of atomic transaction engines including the local atomic transaction engine and a plurality of remote atomic transaction engines; and
send, responsive to the receiving, the information describing the atomic transaction to one or more of the plurality of remote atomic transaction engines to be performed at respective memory addresses of the plurality of different memory addresses controlled by the one or more of the plurality of remote atomic transaction engines.
15. The system of claim 14 , wherein the information describing the atomic transaction to be performed at the plurality of different memory addresses is received from a processor coupled to the local atomic transaction engine responsive to determining that an operation to be executed by the processor targets the plurality of different memory addresses in the distributed shared memory.
16. The system of claim 14 , wherein the local atomic transaction engine is further configured to:
cause performance of a portion of the atomic transaction by the local atomic transaction engine responsive to determining that a memory address of the plurality of different memory addresses of the distributed shared memory is controlled by the local atomic transaction engine.
17. The system of claim 16 , wherein to cause performance of the portion of the atomic transaction, the local atomic transaction engine is configured to:
perform the portion of the atomic transaction by the local atomic transaction engine responsive to determining that the portion of the atomic transaction is performable by circuitry within the local atomic transaction engine without intervention by a processor coupled to the local atomic transaction engine; and
initiate performance of the portion of the atomic transaction by the processor responsive to determining that the atomic transaction is not performable by circuitry within the local atomic transaction engine without intervention by the processor.
18. The system of claim 17 , wherein to initiate performance of the portion of the atomic transaction by the processor, the local atomic transaction engine is configured to:
write the information describing the portion of the atomic transaction into one or more storage locations that are accessible to the processor; and
issue an interrupt to the processor indicating that the atomic transaction should be executed by the processor.
19. The system of claim 18 , wherein the local atomic transaction engine is further configured to:
receive, from the one or more of the plurality of remote atomic transaction engines, respective response data for the request, and in response to the receiving:
return the respective response data to a processor coupled to the local atomic transaction engine; or
writing the respective response data to a location in memory from which the processor expects to retrieve it.
20. The system of claim 14 , wherein the local atomic transaction engine and the plurality of remote atomic transaction engines communicate other over a dedicated low-latency interconnect.