Dual-precision analog memory cell and array
Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.
1. An apparatus comprising:
a dual-precision analog memory cell comprising:
a non-volatile memory element having an input terminal, a first output terminal, and a second output terminal,
a volatile memory element comprising:
a first transistor having a drain electrically coupled to the input terminal of the non-volatile memory element, and
a second transistor having a source electrically coupled to the input terminal of the non-volatile memory element; and
a controller configured to increase a weight stored in the dual-precision analog memory cell by:
biasing a source of the first transistor to a high supply voltage,
biasing a drain of the second transistor to a low supply voltage,
biasing a gate of the second transistor at a low voltage,
biasing the first and second output terminals of the non-volatile memory element at the low voltage, and
applying a high voltage followed by a low voltage pulse to a gate of the first transistor, wherein the high voltage is higher than the low voltage.
2. The apparatus of claim 1 , wherein applying the high voltage followed by the low voltage pulse to the gate of the first transistor charges the input terminal of the non-volatile memory element by a fixed charge q.
3. The apparatus of claim 1 , wherein:
the non-volatile memory element comprises a floating-gate transistor, wherein a gate of the floating-gate transistor is coupled to the input terminal of the non-volatile memory element, and wherein a source and a drain of the floating-gate transistor are coupled to respective ones of the first and second output terminals of the non-volatile memory element.
4. The apparatus of claim 1 , wherein:
the non-volatile memory element comprises a ferro-electric transistor, wherein the ferro-electric transistor comprises a third transistor and a ferroelectric capacitor, wherein the ferroelectric capacitor is coupled between a gate of the third transistor and the input terminal of the non-volatile memory element, and wherein a source and a drain of the third transistor are coupled to respective ones of the first and second terminals of the non-volatile memory element.
5. The apparatus of claim 1 , wherein the non-volatile memory element further comprises:
a third transistor coupled between the gate of the first transistor and a first word line, wherein a gate of the third transistor is coupled to a first bit line; and
a fourth transistor coupled between the gate of the second transistor and a second word line, wherein a gate of the fourth transistor is coupled to a second bit line.
6. The apparatus of claim 1 , wherein:
the first transistor is a first split-gate transistor having a first gate and a second gate, wherein the first gate is coupled to a first word line, and wherein the second gate is coupled to a first bit line; and
the second transistor is a second split-gate transistor having a third gate and a fourth gate, wherein the third gate is coupled to a second word line, and wherein the fourth gate is coupled to a second bit line.
7. A method for increasing a weight stored in a dual precision analog memory cell wherein:
the dual precision analog memory cell comprises:
a dual-precision analog memory cell comprising a non-volatile memory element having an input terminal, a first output terminal, and a second output terminal,
a volatile memory element comprising a first transistor having a drain electrically coupled to the input terminal of the non-volatile memory element, and
a second transistor having a source electrically coupled to the input terminal of the non-volatile memory element; and
the method comprises:
biasing a source of the first transistor to a high supply voltage,
biasing a drain of the second transistor to a low supply voltage,
biasing a gate of the second transistor at a low voltage,
biasing the first and second output terminals of the non-volatile memory element at the low voltage, and
applying a high voltage followed by a low voltage pulse to a gate of the first transistor, wherein the high voltage is higher than the low voltage.
8. The method of claim 7 , wherein applying the high voltage followed by the low voltage pulse to the gate of the first transistor charges the input terminal of the non-volatile memory element by a fixed charge q.
9. The method of claim 7 , wherein:
the non-volatile memory element comprises a floating-gate transistor, wherein a gate of the floating-gate transistor is coupled to the input terminal of the non-volatile memory element, and wherein a source and a drain of the floating-gate transistor are coupled to respective ones of the first and second output terminals of the non-volatile memory element.
10. The method of claim 7 , wherein:
the non-volatile memory element comprises a ferro-electric transistor, wherein the ferro-electric transistor comprises a third transistor and a ferroelectric capacitor, wherein the ferroelectric capacitor is coupled between a gate of the third transistor and the input terminal of the non-volatile memory element, and wherein a source and a drain of the third transistor are coupled to respective ones of the first and second terminals of the non-volatile memory element.
11. The method of claim 7 , wherein the non-volatile memory element further comprises:
a third transistor coupled between the gate of the first transistor and a first word line, wherein a gate of the third transistor is coupled to a first bit line; and
a fourth transistor coupled between the gate of the second transistor and a second word line, wherein a gate of the fourth transistor is coupled to a second bit line.
12. The method of claim 7 , wherein:
the first transistor is a first split-gate transistor having a first gate and a second gate, wherein the first gate is coupled to a first word line, and wherein the second gate is coupled to a first bit line; and
the second transistor is a second split-gate transistor having a third gate and a fourth gate, wherein the third gate is coupled to a second word line, and wherein the fourth gate is coupled to a second bit line.