Imprint management for memory
Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
1. A method, comprising:
writing a first set of logic states to a subset of memory cells of a memory array;
reading, using a reference voltage, the subset of memory cells to obtain a second set of logic states that are based at least in part on the first set of logic states;
determining a quantity of differences between the second set of logic states and the first set of logic states based at least in part on reading at the reference voltage; and
performing a recovery operation on the memory array based at least in part on comparing the quantity of differences to an expected quantity of differences that corresponds to the reference voltage.
2. The method of claim 1 , further comprising:
writing a third set of logic states to a second subset of memory cells of the memory array;
reading, using a second reference voltage, the second subset of memory cells to obtain a fourth set of logic states that are based at least in part on writing the third set of logic states;
determining a second quantity of differences between the fourth set of logic states and the third set of logic states based at least in part on reading using the second reference voltage; and
performing the recovery operation based at least in part on comparing the second quantity of differences to a second expected quantity of differences associated with reading at the second reference voltage.
3. The method of claim 2 , wherein:
the reference voltage is below a default reference voltage for reading memory cells of the memory array; and
the second reference voltage is above the default reference voltage.
4. The method of claim 1 , wherein:
writing the first set of logic states comprises writing a same logic state to each memory cell of the subset of memory cells.
5. The method of claim 1 , further comprising:
reading, prior to writing the first set of logic states to the subset of memory cells, each memory cell of the subset of memory cells to obtain a corresponding initial logic state, wherein each logic state of the first set of logic states differs from the corresponding initial logic state.
6. The method of claim 1 , wherein:
writing the first set of logic states comprises writing a first logic state to a first portion of the subset of memory cells and a second logic state to a second portion of the subset of memory cells.
7. The method of claim 1 , wherein the subset of memory cells comprise a distribution of mixed logic states prior to writing the first set of logic states to the subset of memory cells.
8. The method of claim 1 , wherein writing the first set of logic states to the subset of memory cells comprises:
writing a distribution of mixed data to the subset of memory cells.
9. A method, comprising:
writing a first set of logic states to a subset of memory cells of a memory array;
reading the subset of memory cells to obtain a second set of logic states that are based at least in part on the first set of logic states;
determining that a quantity of differences between the second set of logic states and the first set of logic states satisfies a threshold that is based at least in part on a fixed reference voltage for reading the subset of memory cells; and
performing a recovery operation on the memory array based at least in part on the quantity of differences satisfying the threshold.
10. The method of claim 9 , further comprising:
identifying an activation of the memory array, wherein the writing, reading, and determining are in response to the activation of the memory array; and
performing a plurality of write operations before completion of a boot sequence for a system that includes the memory array.
11. The method of claim 9 , wherein:
writing the first set of logic states comprises writing a same logic state to each memory cell of the subset of memory cells, writing a first portion of the subset of memory cells to a first logic state and a second portion of the subset of memory cells to a second logic state, or a combination thereof.
12. The method of claim 9 , wherein:
a memory device that includes the memory array supports an error-correcting code (ECC) operation for the memory array; and
the threshold is based at least in part on a quantity of errors that are correctable by a codeword associated with the ECC operation.
13. The method of claim 9 , wherein, the subset of memory cells comprise a distribution of mixed logic states prior to writing the first set of logic states to the subset of memory cells.
14. The method of claim 9 , wherein, the threshold is based at least in part on an error tolerance for performing read operations.
15. An apparatus, comprising:
one or more controllers associated with a memory array, wherein the one or more controllers are configured to cause the apparatus to:
write a first set of logic states to a subset of memory cells of the memory array;
read, using a reference voltage, the subset of memory cells to obtain a second set of logic states that are based at least in part on the first set of logic states;
determine a quantity of differences between the second set of logic states and the first set of logic states based at least in part on reading at the reference voltage; and
perform a recovery operation on the memory array based at least in part on comparing the quantity of differences to an expected quantity of differences that corresponds to the reference voltage.
16. The apparatus of claim 15 , wherein the one or more controllers are further configured to cause the apparatus to:
write a third set of logic states to a second subset of memory cells of the memory array;
read, using a second reference voltage, the second subset of memory cells to obtain a fourth set of logic states that are based at least in part on writing the third set of logic states;
determine a second quantity of differences between the fourth set of logic states and the third set of logic states based at least in part on reading using the second reference voltage; and
perform the recovery operation based at least in part on comparing the second quantity of differences to a second expected quantity of differences associated with reading at the second reference voltage.
17. The apparatus of claim 16 , wherein:
the reference voltage is below a default reference voltage for reading memory cells of the memory array; and
the second reference voltage is above the default reference voltage.
18. The apparatus of claim 15 , wherein writing the first set of logic states comprises writing a same logic state to each memory cell of the subset of memory cells.
19. The apparatus of claim 15 , wherein the one or more controllers are further configured to cause the apparatus to:
read, prior to writing the first set of logic states to the subset of memory cells, each memory cell of the subset of memory cells to obtain a corresponding initial logic state, wherein each logic state of the first set of logic states differs from the corresponding initial logic state.
20. The apparatus of claim 15 , wherein writing the first set of logic states comprises writing a first logic state to a first portion of the subset of memory cells and a second logic state to a second portion of the subset of memory cells.